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VHDL-FPGA-Verilog list
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fir
Downloaded:0
Verlog HDL in the use of FPGA realization of FIR filtering, the provision of the relevant parameters can generate module
Date
: 2025-06-27
Size
: 887kb
User
:
libaogang
clock
Downloaded:0
VHDL-based design of the digital clock can be seen directly in the development of on-board results
Date
: 2025-06-27
Size
: 749kb
User
:
lie
alarm
Downloaded:0
(1): the most basic function of time for setup and calibration (2): clock timing, as well as the ringing alarm clock function (3): under certain conditions, the time clock can be achieved automatically modify function (4
Date
: 2025-06-27
Size
: 1kb
User
:
xiaodaselang
fp
Downloaded:0
CSE method are to achieve the FIR digital filter using verilog language written on the back in the real through the ISE
Date
: 2025-06-27
Size
: 1kb
User
:
林萍
ug_ram
Downloaded:0
RAM design for FPGA in verilog
Date
: 2025-06-27
Size
: 283kb
User
:
NguyenViet
Pld_lab4
Downloaded:0
stop watch in vhdl using MAXII development board.
Date
: 2025-06-27
Size
: 1kb
User
:
antish
Ballastic_Calculator
Downloaded:0
Ballastic Calculator Interface designe for Army TANK (Xilinx Verilog, Schematics)
Date
: 2025-06-27
Size
: 2.57mb
User
:
Tomahawk
BCD
Downloaded:0
BCD digital display in the DE2 platform quartus
Date
: 2025-06-27
Size
: 56kb
User
:
johnson
lift
Downloaded:0
(1) the realization of four-storey elevator with VHDL controller operation. (2) elevator button with a lock to run in place of (unlock power), low run, can not run high. (3) on each floor with elevator at the entrance to
Date
: 2025-06-27
Size
: 283kb
User
:
管皮皮
lonely
Downloaded:0
1 code table
Date
: 2025-06-27
Size
: 566kb
User
:
吳員外
mc8051
Downloaded:0
source code of the implement of 8051,by the source code ,we can learn the implement principle of 8051 CPU
Date
: 2025-06-27
Size
: 197kb
User
:
xu_xf
counter
Downloaded:0
the difference counter ,it can help to learn VHDL ,it can also be as a modular in your project
Date
: 2025-06-27
Size
: 1kb
User
:
xu_xf
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.87
.88
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.90
.91
3592
.93
.94
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.96
.97
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4310
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