VHDL-FPGA-Verilog List Page 354

VHDL-FPGA-Verilog list

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PS2shubiao Downloaded：0: PS2 mouse project based on FPGA
Date : 2025-12-30 Size : 539kb User : liagnlin
Stopwatch Downloaded：0: In quatus platform, verilog language stopwatch code. Achieve functional start, pause, reset, pause the display. On Cyclone2 run through.
Date : 2025-12-30 Size : 6.3mb User : 王健
chuzuche Downloaded：0: Taxi vhdl program, with a testbench simulation program, started by the reset button, then the exercise kilometer count signal, starting at 3 km 8 yuan, more than three kilometers one kilometer dollar.
Date : 2025-12-30 Size : 552kb User : huawei
can-sja1000 Downloaded：0: The FPGA and the sja1000 CAN bus development code, communication, which CAN realize the CAN send and receive.
Date : 2025-12-30 Size : 522kb User : 孙海洋
cgra-full Downloaded：0: verilog code for cgra architecture
Date : 2025-12-30 Size : 26kb User : rajesh
bus-invertcoding Downloaded：0: verilog code for bus invert coding
Date : 2025-12-30 Size : 55kb User : rajesh
fibonaccicode Downloaded：0: verilog code for fibonacci codes
Date : 2025-12-30 Size : 5kb User : rajesh
floating-point-multip Downloaded：0: verilog code for floating point multiplier
Date : 2025-12-30 Size : 50kb User : rajesh
random_num Downloaded：0: Random number generation
Date : 2025-12-30 Size : 832kb User : mproject
Array_slice_1Dx1D_of-bit-vector Downloaded：0: Array slice 1dx1D for individual access of element
Date : 2025-12-30 Size : 91kb User : mproject
RAM1 Downloaded：0: Ram source code 32-bit.
Date : 2025-12-30 Size : 475kb User : mproject
MatrixAdd Downloaded：0: Matrix addition for matrix operation
Date : 2025-12-30 Size : 40kb User : mproject

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