VHDL-FPGA-Verilog List Page 3492

VHDL-FPGA-Verilog list

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EPM240_SCH_and_program Downloaded：0: Schematic diagram+ EPM240 cpld procedures. Sine wave generator procedures, ADC0804 DC sampling and showed that Chinese scroll, traffic lights, keyboard, display program, counters and so on.
Date : 2025-07-03 Size : 645kb User : student88
systemverilog Downloaded：1: system verilog is popular hardware design and verification language. The languange compose of two part: systemverilog for desin , system verilog for test . in the rar package , a book introducing system verilog is recomm
Date : 2025-07-03 Size : 5.83mb User : jhv
verilog_pli Downloaded：0: Pli system fuction is used in verilog language, but material related pli in domestic is rare. the rar package is my collection on pli , hop it is useful.:)
Date : 2025-07-03 Size : 2.13mb User : jhv
ep_rom Downloaded：0: VerilogHdl the use of languages, ranging from the development of FPGA to read and write the EPROM
Date : 2025-07-03 Size : 1kb User : Kevin Yu
Generatedsinewave Downloaded：0: The process of downloading to the FPGA to enable it to have a sine wave, which can achieve its work months
Date : 2025-07-03 Size : 6kb User : zjs
demtang09 Downloaded：0: the proramme is created to be examble to leran verilog programming. it s porpuse is crease the number is 7-segment from 0 to 9.
Date : 2025-07-03 Size : 314kb User : connit1986
dem4bit_hienthi Downloaded：0: the verilog source code for being an examble to counts 4-bit number and display in 7-segment.
Date : 2025-07-03 Size : 311kb User : connit1986
alu Downloaded：0: The examble to discribe a simple ALU.
Date : 2025-07-03 Size : 250kb User : connit1986
DDS Downloaded：0: Our group for a month to do a total of DDS, the procedure is used in the core of Verilog HDL, there are simulation waveform, the output sine wave, square wave and triangular wave, step adjustable. Frequency range 1HZ- 10
Date : 2025-07-03 Size : 115kb User : tiancheng
10100MIP Downloaded：0: 10100M IP Ethernet core Verilog source code (which can be integrated) \ 10-100M IP Ethernet core Verilog source code can be integrated
Date : 2025-07-03 Size : 723kb User : 打狗队
Verilog_135example Downloaded：0: Verilog design 135 Classic examples include the commonly used procedure, function, etc.
Date : 2025-07-03 Size : 111kb User : iPhoenix
hello_world Downloaded：0: On the NIOS infrared remote control code, may be interested in playing under the
Date : 2025-07-03 Size : 1kb User : iPhoenix

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