VHDL-FPGA-Verilog List Page 3459

VHDL-FPGA-Verilog list

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my-favorite-dc-primetime-tcl-tricks Downloaded：0: sta training
Date : 2025-07-22 Size : 155kb User : yoarst
perl Downloaded：0: perl training
Date : 2025-07-22 Size : 1.44mb User : yoarst
DenaliTechDayPresentation Downloaded：0: denali memory controller
Date : 2025-07-22 Size : 11.35mb User : yoarst
ovm-1[1].0.1.tar Downloaded：0: ovm verfication package
Date : 2025-07-22 Size : 738kb User : yoarst
OVM_Datasheet_12-17-07_introduction Downloaded：0: ovm datasheet
Date : 2025-07-22 Size : 268kb User : yoarst
ProtelDesignInVHDL Downloaded：0: Protel design in VHDL
Date : 2025-07-22 Size : 114kb User : 李东
FPGAvhdl Downloaded：0: FPGA embedded applications a typical example of system development
Date : 2025-07-22 Size : 12.55mb User : 李东
fenpinqi Downloaded：0: Divider design using VHDL language requirement will be 128 Hz pulses were generated through divider 64 Hz, 32 Hz, 16 Hz, 8 Hz, 4 Hz, 2 Hz, 1 Hz, 0.5 Hz frequency of the eight kinds of signal
Date : 2025-07-22 Size : 1kb User : 高原
dds Downloaded：0: DA convert
Date : 2025-07-22 Size : 1kb User : huruifang
lcd1602 Downloaded：0: lcd1602 the reality of the procedure, you can scan the screen line by line
Date : 2025-07-22 Size : 1kb User : 刘峰
iic Downloaded：0: Cpld single-chip computer and communications cpld prepared using vhdl source code
Date : 2025-07-22 Size : 1kb User : 高原
SPWM Downloaded：0: Cpld developed by spwm waves on the generation of vhdl code
Date : 2025-07-22 Size : 345kb User : 高原

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