VHDL-FPGA-Verilog List Page 3438

VHDL-FPGA-Verilog list

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dds Downloaded：0: VHDL compiled CPLD sine wave generation process by direct numerical synthesis of theory-driven dac0832 achieved DDS sine wave input
Date : 2025-07-15 Size : 2kb User : 袁文鼎
vhdlprogrammes Downloaded：0: vhdl programmes of state machine
Date : 2025-07-15 Size : 3kb User : sachy
s2p Downloaded：0: A string and convert the Verilog source code, there are questasim simulation.
Date : 2025-07-15 Size : 117kb User : 杨经纬
test Downloaded：0: All appropriated for the DIP switch on, will see the digital tube display one by one from the 0-9 AF press 8 keys in any one, the corresponding LED lantern light, according to the first button, the buzzer will ring for .
Date : 2025-07-15 Size : 138kb User : panda
pwmtest Downloaded：0: DIP switch control PWM duty cycle is 16, corresponding to voltage of 3.3 volts, one of the 16 sub-multiples
Date : 2025-07-15 Size : 171kb User : panda
sensortest Downloaded：0: Light sensors measure the ambient light LED will show the size, hands blocking the light sensor, LED display the value of a corresponding decrease.
Date : 2025-07-15 Size : 187kb User : panda
test Downloaded：0: All appropriated for the DIP switch on, will see the digital tube display one by one from the 0-9 AF press 8 keys in any one, the corresponding LED lantern light, according to the first button, the buzzer will ring for .
Date : 2025-07-15 Size : 130kb User : panda
PWMtest Downloaded：0: DIP switch to an analog signal PWM switch control PWM duty cycle is 16, corresponding to voltage of 3.3 volts, one of the 16 sub-multiples
Date : 2025-07-15 Size : 137kb User : panda
sensortest Downloaded：0: Light sensor: LED ambient light will show the size, hands blocking the light sensor, LED display the value of a corresponding decrease.
Date : 2025-07-15 Size : 291kb User : panda
altera_mf Downloaded：0: HD or SD I signals, through the development of the FPGA-Audio procedures.
Date : 2025-07-15 Size : 9kb User : 邢占鹏
example1 Downloaded：0: To achieve the clock signal clk is the frequency function is available through the waveform simulation to evaluate the effects.
Date : 2025-07-15 Size : 29kb User : panda
example2 Downloaded：0: moore state machine processes a total of four conditions, idle idle wait for ready signal ready to enter the state decision or sentence to wait for ready signal ruling the state decision will oe, we set the signal low, b
Date : 2025-07-15 Size : 31kb User : panda

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