VHDL-FPGA-Verilog List Page 3421

VHDL-FPGA-Verilog list

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key Downloaded：0: du to fpga 4*4 keyscan verilog
Date : 2025-07-16 Size : 1kb User : fds
IIC_slave_code Downloaded：0: about I2C slave code about I2C slave code
Date : 2025-07-16 Size : 181kb User : qinjuanyan
s3ansk_paint Downloaded：0: Paint for SPARTAN 3E
Date : 2025-07-16 Size : 846kb User : atcam
ActivePowerMeter Downloaded：0: Spartan 3e- Active Power Meter
Date : 2025-07-16 Size : 55kb User : atcam
key Downloaded：0: Written in Verilog HDL keyboard scanner, taking into account to determine key bounce problem. Program according to a certain frequency of scan lines with low-level circulation lines, while testing out the state line, onc
Date : 2025-07-16 Size : 2.1mb User : 力文
ddfsdemo Downloaded：0: Direct Digital Frequency Synthesizer ( DDFS) of the VHDL program, the development environment is QuartusII, the system clock to 50MHz, the work of DDFS generated by PLL clock 166.67MHz, address bit-width of 24-bit freque
Date : 2025-07-16 Size : 632kb User : 力文
clock_digital Downloaded：0: Written by Verlog HDL ，a digital clock program, including hours, minutes, seconds, into the place, decoding, scanning display.
Date : 2025-07-16 Size : 1008kb User : 吴海燕
VHDLquickstart Downloaded：0: Quick introduction to VHDL – basic language concepts – basic design methodology • Use The Student’s Guide to VHDL or The Designer’s Guide to VHDL – self-learning for more depth – reference for project work
Date : 2025-07-16 Size : 79kb User : yag
Verilog Downloaded：0: verilog
Date : 2025-07-16 Size : 605kb User : 柳澈
1_ADDER Downloaded：0: vhdl　adder vhdl　adder vhdl　adder
Date : 2025-07-16 Size : 22kb User : jiang
Verilog Downloaded：0: verilog
Date : 2025-07-16 Size : 39kb User : 柳澈
verilogFIR Downloaded：0: verilog
Date : 2025-07-16 Size : 624kb User : 柳澈

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