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VHDL-FPGA-Verilog list
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verilog to achieve a " parallel input, parallel output shift register"
Date : 2025-07-14 Size : 1kb User : 王先生

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verilog implementation " BCD/Seven-Segment Decoder."
Date : 2025-07-14 Size : 1kb User : 王先生

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modelsim tutorial to learn only
Date : 2025-07-14 Size : 475kb User : 王先生

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verilog implementation of the " six hexadecimal Johnson counters."
Date : 2025-07-14 Size : 2kb User : 王先生

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verilog to achieve a " state machine to achieve AD574 digital-analog conversion"
Date : 2025-07-14 Size : 1kb User : 王先生

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verilog to achieve a " state machine to achieve AD0809 digital to analog conversion."
Date : 2025-07-14 Size : 1kb User : 王先生

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VHDL
Date : 2025-07-14 Size : 6kb User : coolxgz

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Based on Actel A3P030 FPGA, LCD using JDL12864 serial interface, clock 48MHz
Date : 2025-07-14 Size : 4kb User : songxin

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VHDL language is to use FPGA-based uart source code!
Date : 2025-07-14 Size : 62kb User : 陈涛

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Based on FPGA chip, the Nios II IDE software development environment written in NIos II soft-core uart source code!
Date : 2025-07-14 Size : 340kb User : 陈涛

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Pinson prepared by the EDA books! Learning FPGA a good helper!
Date : 2025-07-14 Size : 8.95mb User : 陈涛

there are exemple in the vhdl
Date : 2025-07-14 Size : 10kb User : tarik
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