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VHDL-FPGA-Verilog list
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VHDL code to digitally control the interface with a VGA display. Code is technologically independent and can be prototyped in any programmable device or ASIC.
Date : 2025-07-22 Size : 2kb User : celia

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source I2c controller WB uC bus plus alternative controlling- verilog code
Date : 2025-07-22 Size : 117kb User : rozenan

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this is the 1 bit counter clock where the counter increase by 1 on rising edge clock
Date : 2025-07-22 Size : 104kb User : law

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4 bit fpga code for beginner
Date : 2025-07-22 Size : 129kb User : law

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single bit full adder
Date : 2025-07-22 Size : 134kb User : law

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single bit half adder
Date : 2025-07-22 Size : 120kb User : law

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seven segment simple coding
Date : 2025-07-22 Size : 113kb User : law

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Huaqing vision FPGA Part 2, FPGA design entry-2 video
Date : 2025-07-22 Size : 5.54mb User : 林方

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good verilog for crc,is good for fpga.welcome to down
Date : 2025-07-22 Size : 1kb User : sxh

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Huaqing vision video, FPGA Introduction Video Part 4 of the second stress
Date : 2025-07-22 Size : 8.86mb User : 林方

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EPM240+ IS61LV1024+ VERILOG to achieve LED display control, 1 red+ 1 green, and 1280* 512, and AT91SAM7S64 Interface
Date : 2025-07-22 Size : 553kb User : 刘聪

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Asynchronous signals using synchronous way, two a clock CLK to the same uniform to work, using synchronous FIFO Asynchronous FIFO
Date : 2025-07-22 Size : 3kb User : 范小虎
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