VHDL-FPGA-Verilog List Page 3318

VHDL-FPGA-Verilog list

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motor3_and_motor4 Downloaded：0: Program is CPLD pairs of counter procedures, mainly for motor encoder counts
Date : 2025-07-16 Size : 845kb User : 王川
encode Downloaded：0: Shaft encoder to achieve the procedure, control is more useful oh
Date : 2025-07-16 Size : 888kb User : dongbin
verilogHDL Downloaded：0: With the Verilog HDL language to achieve universal asynchronous receiver URAT Device
Date : 2025-07-16 Size : 26kb User : chenke
10_100m_ethernet-fifo_convertor_latest.tar Downloaded：0: 10_100m_ethernet-fifo_convertor_latest, using the verilog language to write, please refer to the needs of down and not used for commercial, thank you!
Date : 2025-07-16 Size : 558kb User : 磊
quartusII8.0_crack Downloaded：0: quartusII8.0 software use license, you must learn from a friend can put to use, not rumor, thank you
Date : 2025-07-16 Size : 15kb User : 磊
book Downloaded：0: A VHDL good book, which describes how to use VHDL to do the number of electrical experiments!
Date : 2025-07-16 Size : 887kb User : 陈亮
ADS7852 Downloaded：0: FPGA and ADS7852
Date : 2025-07-16 Size : 234kb User : xila
fifo2 Downloaded：0: VHDL and fifo
Date : 2025-07-16 Size : 195kb User : xila
M-sequence-generator Downloaded：0: M sequence generator
Date : 2025-07-16 Size : 207kb User : jkl
BIN_CV_MEN Downloaded：0: 2 into digital files can be converted to a text file for verilog applications
Date : 2025-07-16 Size : 1kb User : Henry
yinbo Downloaded：0: Password lock, enter the correct password the door opened the wrong password lights, continuous input an incorrect password three times, alarm sound, until you enter the correct password
Date : 2025-07-16 Size : 1kb User : 殷波
12 Downloaded：0: A digital clock that can display minutes and seconds, the whole point timekeeping, poor start 10 seconds the whole point timekeeping.
Date : 2025-07-16 Size : 1kb User : 殷波

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