VHDL-FPGA-Verilog List Page 3288

VHDL-FPGA-Verilog list

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simple_3DES Downloaded：0: reduced 3DES algorithm system based on FPGA
Date : 2025-07-16 Size : 2.67mb User : dinxj
crc Downloaded：0: High-speed multi-channel crc implementation, can be achieved in parallel 5-channel data validation, support for 10GB Ethernet standard
Date : 2025-07-16 Size : 44kb User : dinxj
cordic Downloaded：0: Rotating coordinates high-speed computer hardware algorithm for fast Fourier algorithm is the core unit
Date : 2025-07-16 Size : 27kb User : dinxj
color_space_converters Downloaded：0: Color space conversion hardware for image processing, encoding, decoding part of the
Date : 2025-07-16 Size : 2.49mb User : dinxj
aes Downloaded：0: Advanced Encryption Standard AES, FPGA implementation to support 128,256 key length format
Date : 2025-07-16 Size : 85kb User : dinxj
jifei Downloaded：0: In the Quartus environment, the use of VHDL language taxi billing system, the system is divided into sub-frequency, state switching, recording process, billing and other modules, to imitate reality, taxi billing.
Date : 2025-07-16 Size : 1.5mb User : wahu
liushuideng Downloaded：0: led s hdl describe
Date : 2025-07-16 Size : 1kb User : blackstone
Multi-networkvideocallsource Downloaded：0: DE2-based video telephony part of the source code to achieve the video image capture, VGA display, LAN communications function
Date : 2025-07-16 Size : 19kb User : lizhijie
DATA_scramble Downloaded：0: Scrambler in verilog implementation
Date : 2025-07-16 Size : 1kb User :
ctrl1 Downloaded：0: mimasuo
Date : 2025-07-16 Size : 1kb User : mengqingan
paomadenghe60jinzhi Downloaded：0: Marquee with a program written in VHDL, and 60 binary counter program, one designed by one teacher asked, are in the experimental boxes proved to be successful, want to help everyone.
Date : 2025-07-16 Size : 251kb User : zhangliang
chengfaqi Downloaded：0: Multiplier to achieve the functions of multiplication and division to carry out 32-bit computing
Date : 2025-07-16 Size : 4.94mb User : 风清扬

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