VHDL-FPGA-Verilog List Page 3212

VHDL-FPGA-Verilog list

Sort by ：

« 1 2 ... .07 .08 .09 .10 .11 3212.13 .14 .15 .16 .17 ... 4310 »

turbocodes_latest.tar Downloaded：0: turbo encode and decoder
Date : 2025-07-27 Size : 82kb User : suresh
t1 Downloaded：0: tourbo encode pdf file we can study derive these folders
Date : 2025-07-27 Size : 124kb User : suresh
arm9_fpga2_verilog Downloaded：0: arm9 FPGA VERILOG code
Date : 2025-07-27 Size : 192kb User : 马骥
EnergyEfficientVLSIArchitectureforLinearTurboEqua Downloaded：0: Energy efficient for turbo encoder decoder
Date : 2025-07-27 Size : 524kb User : suresh
IterativeDecodingofBinary Downloaded：0: In this paper, energy efficient VLSI architectures for linear turbo equalization are studied. Linear turbo equalizers exhibit dramatic bit error rate (BER) improvement over conventional equalizers by enabling a form of j
Date : 2025-07-27 Size : 1.45mb User : suresh
MapAlgorithm Downloaded：0: However, turbo equalizers can be computationally complex and hence require significant power consumption. In this paper, we present an energy-efficient VLSI architecture for such linear turbo equalizers. Key architectura
Date : 2025-07-27 Size : 1.25mb User : suresh
RECURSIVEALGORITHMFOREFFICIENTMAPDECODING Downloaded：0: Early termination enables powering down parts of the soft-input soft-output (SISO) equalizer and decoder thereby saving power.
Date : 2025-07-27 Size : 102kb User : suresh
VerilogLangRefManual Downloaded：0: Simulation results show that energy savings in the range 30–60 and 10–60 are achieved in equalization and decoding, respectively. Furthermore, we present finite precision requirements of the linear turbo equalizer and an
Date : 2025-07-27 Size : 1.22mb User : suresh
CPU Downloaded：0: CPU
Date : 2025-07-27 Size : 2.46mb User : 姚琪儿
polyphase Downloaded：0: The current portion of the collaboration has involved the feasibilty and implementation of a Polyphase Filter bank using various FPGAs and hardware architectures
Date : 2025-07-27 Size : 267kb User : vadik
AD6635 Downloaded：0: The AD6635 is a multimode, 8-channel, digital Receive Signal Processor (RSP) capable of processing up to four WCDMA channels
Date : 2025-07-27 Size : 497kb User : vadik
ip_digifrec Downloaded：0: The Digital IF Receiver megafunction combines a quadrature NCO and a digital mixer to translate the input IF signal down to baseband
Date : 2025-07-27 Size : 67kb User : vadik

« 1 2 ... .07 .08 .09 .10 .11 3212.13 .14 .15 .16 .17 ... 4310 »

Search in result