VHDL-FPGA-Verilog List Page 3203

VHDL-FPGA-Verilog list

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latch Downloaded：0: Latch VDHL by xilinx
Date : 2025-07-28 Size : 262kb User : mohab
counter Downloaded：0: Ring Counter implemented in VHDL usign finite state machine design.
Date : 2025-07-28 Size : 1kb User : slash
ADC124 Downloaded：0: Verilog prepared using high-speed string-type AD Acquisition chip adc124 driver code, occupation le small, high efficiency, the current I applied to more products
Date : 2025-07-28 Size : 1kb User : chenwl
dac121 Downloaded：0: Verilog prepared using high-speed string-type DA-chip dac121 driver code, occupation le small, high efficiency, the current I applied to more products
Date : 2025-07-28 Size : 336kb User : chenwl
ds18b20 Downloaded：1: Single DS18B20 the verilog HDL code, and an accuracy of 1 ℃ without converting the data, direct output. Occupy 300 LE resources.
Date : 2025-07-28 Size : 433kb User : chenwl
ds18b20s4 Downloaded：0: Four DS18B20 the verilog HDL code, and an accuracy of 1 ℃ without converting the data, enter the address change in accordance with the direct output. Occupy 600 LE resources, as opposed to one-way process, a more streaml
Date : 2025-07-28 Size : 433kb User : chenwl
ds18b20s16 Downloaded：0: 16 DS18B20 the verilog HDL code, and an accuracy of 1 ℃ without converting the data, direct output. Occupy 1100 LE resources. Suitable for multi-channel probe with the same time, require a shorter acquisition cycle progr
Date : 2025-07-28 Size : 433kb User : chenwl
tlc2543AND11channel Downloaded：0: 11-Channel Serial AD acquisition chip TLC2543, 12BIT accuracy of the output, 100Khz, using VERILOG HDL preparation, taking up 200 LE
Date : 2025-07-28 Size : 32kb User : chenwl
mypjct Downloaded：0: One' s own design, using verilog language implementation of the design of an automatic vending machine
Date : 2025-07-28 Size : 68kb User : yanping
ntc Downloaded：0: NTC resistor VERILOG HDL in the curve of the table, use the 1MA current source power supply voltages were collected with AD and in the form of the output look-up table 12BIT can be achieved by the actual temperature valu
Date : 2025-07-28 Size : 88kb User : chenwl
divider Downloaded：0: a clock divider vhdl code
Date : 2025-07-28 Size : 231kb User : mansih
vhdl_serial_receiver Downloaded：0: a good serial receiver in vhdl , there is also transmitter code along with this , check it in same web
Date : 2025-07-28 Size : 208kb User : mansih

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