VHDL-FPGA-Verilog List Page 3195

VHDL-FPGA-Verilog list

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DataCap_XKL_sw_0309_UCGUI_fine Downloaded：0: Using xilinx provides xilkernel system, including ucGUI, an increase of custom keyboard and LCD screen support.
Date : 2025-07-28 Size : 4.18mb User : xjtualex
Microprogramcontroller Downloaded：0: Micro-program controller component experiments, the use of VHDL language use Quartus test, simulation CPU
Date : 2025-07-28 Size : 735kb User : 糖糖
riscfile Downloaded：0: This program focuses on a risc processor, the basic functional unit of the procedures and documentation and hope for all of us
Date : 2025-07-28 Size : 157kb User : 田雨
clock Downloaded：0: Stopwatch' s verilog language implementation, personal curriculum design, code, and has been verified! Implementation show seconds, minutes, suspended, amendment and other functions.
Date : 2025-07-28 Size : 2kb User : 张文宝
CANProtocolControllerIPCoreinVerilog Downloaded：1: CAN Protocol Controller IP Core in Verilog.
Date : 2025-07-28 Size : 66kb User : Nicholas
SIGNAL_GEN Downloaded：0: The use of EDA, VHDL hardware description language design function of the signal generator can generate increased progressively decreasing ramp, triangle wave, step-wave, sine wave, square wave
Date : 2025-07-28 Size : 507kb User : 心心
crc8_4 Downloaded：0: crc8 datawidth 4 verilog
Date : 2025-07-28 Size : 1kb User : chenk
crc12_4 Downloaded：0: crc12 datawidth is 4，coding by verilog
Date : 2025-07-28 Size : 1kb User : chenk
crc16_8 Downloaded：0: crc16 ,datawidth is 8,coding by verilog
Date : 2025-07-28 Size : 1kb User : chenk
crc32_8 Downloaded：0: crc32，datawidth is8,coding by verilog
Date : 2025-07-28 Size : 1kb User : chenk
crc_ccit_8 Downloaded：0: crc_ccit, datawidth is 8,coding by verilog
Date : 2025-07-28 Size : 1kb User : chenk
AD Downloaded：0: ADC0809 based data acquisition system, for 0 ~ 5V voltage of the collection, display to the digital tube display
Date : 2025-07-28 Size : 1kb User : liuyong

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