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VHDL-FPGA-Verilog list
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Computer Organization and Architecture Designing for Performance Experiment
Date : 2025-07-28 Size : 259kb User : 欧泽林

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Implemented using vhdl digital clock, with the whole point timekeeping, transfer-time functionality.
Date : 2025-07-28 Size : 186kb User : 王瑞

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Responder using vhdl implementation, can achieve 20 seconds to answer in the countdown, fouls alarm, reset, scoring functions.
Date : 2025-07-28 Size : 257kb User : 王瑞

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On cpld frequency counter program, measurement frequency range of 1Hz to 99999Hz
Date : 2025-07-28 Size : 149kb User : 心蓝海

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Quartus8.1 created using the company' s EP2C8 based ALter liquid crystal display a picture of the 12864 complete project file.
Date : 2025-07-28 Size : 148kb User : 胡丹

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the map of cpld developed board。
Date : 2025-07-28 Size : 93kb User : c67890

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FPGA code for analogue and digital conversion,which has been tested with hardware.
Date : 2025-07-28 Size : 1kb User : yangyanwen

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Vhdl coding using filter simulation, there is some help for beginners.
Date : 2025-07-28 Size : 1.09mb User : 韩亦勇

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Use VerilogHDL language programming 8051 microcontroller functions in FPGA projects in a wide range of applications
Date : 2025-07-28 Size : 51kb User : luosheng

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Parallel data streams into a special kind of serial communication protocol data stream focuses on the realization of the same clock-driven attention to a few signals, if signals need to separate the use of hopping along
Date : 2025-07-28 Size : 444kb User : luosheng

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This process is complete a sequence of test functions, test 10010 sequence, appropriate improvements can be used for FPGA in the signal detection
Date : 2025-07-28 Size : 215kb User : luosheng

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In the FPGA to achieve a FIR filter, appropriate changes to filter parameters, you can apply your own project
Date : 2025-07-28 Size : 435kb User : luosheng
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