VHDL-FPGA-Verilog List Page 3076

VHDL-FPGA-Verilog list

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pll Downloaded：0: HSPICE PLL circuit for HSPICE to provide the demo program.
Date : 2025-11-16 Size : 1kb User : 邹洲
XCFxxP Downloaded：0: eeprom for fpga sparten 3
Date : 2025-11-16 Size : 473kb User : farshid
spi Downloaded：0: 基于CPLD的用SPI控制pwm的源码，用VHDL编写，已经测试，可以直接使用
Date : 2025-11-16 Size : 1kb User : DRzhou
VGA_COLOUR Downloaded：0: vga CONTROL ip nuclear
Date : 2025-11-16 Size : 6kb User : 智日
sc_examples.tar Downloaded：0: some examples of SystemC to begin SoC modeling
Date : 2025-11-16 Size : 1.6mb User : mizmiz
data_rom Downloaded：0: sine wave signal generator sine wave signal generator
Date : 2025-11-16 Size : 1kb User : 闫普
MII_timing Downloaded：0: implementation of MII data transmission’s timing control
Date : 2025-11-16 Size : 2kb User : 刘强为
max Downloaded：0: This is a counter above the MAX+ plus simulation map, FPGA-based simulation.
Date : 2025-11-16 Size : 18kb User : 王天刚
MEdia_control_i2c Downloaded：0: Will come from the MAC' s GMII8B codes 8B/10B encoding. FPGA output 10 Road 10B code data, if necessary, can be configured to plug SDRAM, FPGA have to realize SDRAM controller
Date : 2025-11-16 Size : 35kb User : 刘强为
tristtes_test Downloaded：0: Three-state gate FPGA Programming is often encountered a problem, we design a proper simulation method, we want to help
Date : 2025-11-16 Size : 5kb User : 刘强为
FrequencyMeasureV1.0 Downloaded：0: Verilog of frequency measurement
Date : 2025-11-16 Size : 415kb User : 潘阳
hongwai Downloaded：0: Transmitter is composed of 555 core multivibrator, by changing the oscillator frequency to adjust the frequency of infrared emitter, and can adjust the resistance to reduce the infrared signal duty cycle to increase as m
Date : 2025-11-16 Size : 108kb User : 徐彬

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