VHDL-FPGA-Verilog List Page 2885

VHDL-FPGA-Verilog list

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clk_counter Downloaded：0: clk_counter
Date : 2025-11-20 Size : 1kb User : 孙浩源
lcd_fpga Downloaded：0: Application DE0 NIOSII environment in hardware platform, achieving in the LCD display on the character and the character seven-segment display decoder
Date : 2025-11-20 Size : 1kb User : 秦金文
EPM570 Downloaded：0: This the EPM570 ATLREA a minimum of 144 pin CPLD system diagram, for the design of the board has the role of CPLD
Date : 2025-11-20 Size : 333kb User : yuanzengquan
eth_crc Downloaded：0: crc checksum Verilog program. This is a 4-bit parallel crc- 32 check.
Date : 2025-11-20 Size : 2kb User : hepeng
crc_testbench Downloaded：0: This is the crc test bench file. Main environment is modelsim. Apply to beginners
Date : 2025-11-20 Size : 357kb User : hepeng
ampliFM100W Downloaded：0: 100w Amplifier very powerful
Date : 2025-11-20 Size : 61kb User : Amir
VHDLnew Downloaded：0: vhdl book by douglas berry
Date : 2025-11-20 Size : 1.7mb User : shahul
symbolsandnumericaldecomposition Downloaded：0: verilog for symbols and numerical decomposition
Date : 2025-11-20 Size : 4.1mb User : wangyang
i2c Downloaded：0: Standard I2c read and write timing, verilog Hdl
Date : 2025-11-20 Size : 3kb User : wangminghui
FPGAtestpapers Downloaded：0: fpga document is full on-line order of questions, we want to help
Date : 2025-11-20 Size : 172kb User : yuyong
Alteradesigndocument Downloaded：0: The experimental procedure for each project examples include the works of the project file, source documents, reports and other documents file and generate the results, the reader can use Quartus II or directly open the
Date : 2025-11-20 Size : 49.81mb User : caozh
Example-b3-1 Downloaded：0: Each project examples include the project files of the project, source files, report files and generate the results files, the reader can use Quartus II or the software to directly open the corresponding. Design source f
Date : 2025-11-20 Size : 1.1mb User : caozh

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