VHDL-FPGA-Verilog List Page 2724

VHDL-FPGA-Verilog list

Sort by ：

« 1 2 ... .19 .20 .21 .22 .23 2724.25 .26 .27 .28 .29 ... 4310 »

PN4 Downloaded：0: Language: VHDL function: the sequence characteristics of the PN4 a 4-bit sequence of the first two to take different or, let a sequence of left, with the result as a sequence of different or the last one. Sequence cycle
Date : 2025-11-21 Size : 4kb User : huangjiaju
SRAM Downloaded：0: Language: VHDL function: the use of VHDL programming, FPGA on SRAMIS61LV24516 read and write operations. Because it is read and write for IS61LV24516 model, if not required for this type of SRAM timing of the program cha
Date : 2025-11-21 Size : 1kb User : huangjiaju
DDS-SIN Downloaded：0: DDS based on the principle of amplitude, frequency tunable sine wave generator that contains 1602 microcontroller read the keyboard and display program
Date : 2025-11-21 Size : 8.57mb User : weiwenfeng
I2C Downloaded：0: Language: verilog Function: I2C written in Verilog HDL with the host serial communication program. Two bus lines: a serial data line SDA, a serial clock line SCL 8-bit bi-directional serial data transmission bit rate in
Date : 2025-11-21 Size : 8kb User : huangjiaju
VHDLDigitalClock Downloaded：0: Digital clock in the VHDL language for basic functions, including 1,24-hour count display 2, when a school function (hour, minute) additional requirements: 1, to achieve the alarm function (time, alarm sound)
Date : 2025-11-21 Size : 1kb User : xiezunzhong
FSM Downloaded：0: Finite state machine, with the Verilog language, the implementation of the right, simulation pass.
Date : 2025-11-21 Size : 332kb User : uyuy0401
isa Downloaded：0: Computer Organization and curriculum lab reports, there are specific instructions design ideas.
Date : 2025-11-21 Size : 1.66mb User : uyuy0401
alu Downloaded：0: ALU implementation, the use of Veriolog language, programming, error-free, smooth build, executable, simulation plan correctly ~
Date : 2025-11-21 Size : 215kb User : uyuy0401
move Downloaded：0: Barrel shifter, the use of Verilog language, programming, simulation is correct, the successful implementation.
Date : 2025-11-21 Size : 306kb User : uyuy0401
Reg16 Downloaded：0: Register realization of the principle, 16, Verilog language, the simulation successfully.
Date : 2025-11-21 Size : 381kb User : uyuy0401
DE2_CCD_sobel Downloaded：0: Extraction of the image through the camera, in the FPGA implementation of the development board, the main achievement of the image contour extraction
Date : 2025-11-21 Size : 251kb User : 枫雪
z_motor_driver Downloaded：0: VERILOG brushless DC drive module can be further improved and optimized. Has been tested
Date : 2025-11-21 Size : 2kb User : tcw822

« 1 2 ... .19 .20 .21 .22 .23 2724.25 .26 .27 .28 .29 ... 4310 »

Search in result