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VHDL-FPGA-Verilog list
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Preset function in parallel with synchronous 8-bit left shift register
Date : 2025-11-21 Size : 189kb User : 张敏

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8-bit binary value of the comparator, which is used in the verilog hdl behavioral modeling language to write
Date : 2025-11-21 Size : 144kb User : 黄启

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Which contains a number of previously written a variety of learning adder and HDB3 encoding, and the state machine of some of the topics
Date : 2025-11-21 Size : 2.13mb User : yuandb

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Filter by language VHDL design and simulation through modelsim! Results with matlab generate input and output compared with the matlab are the same.
Date : 2025-11-21 Size : 339kb User : weihli

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EDA数字时钟设计程序报告!!!!!!!!!!!!!!!!!!
Date : 2025-11-21 Size : 284kb User : WEB

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wm8731 I2S audio capture chip timing acquisition vhdl implementation.
Date : 2025-11-21 Size : 2kb User : 熊晓涵

- A Programming Example_Large FFT
Date : 2025-11-21 Size : 67kb User : huuhung

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- CORDIC for sine cosine computation
Date : 2025-11-21 Size : 281kb User : huuhung

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- FFTs_in_FPGAs_and_ASICs
Date : 2025-11-21 Size : 48kb User : huuhung

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Verilog exam
Date : 2025-11-21 Size : 72kb User : yangfan

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LED display verilog code. to generate clocks and wishbone interface
Date : 2025-11-21 Size : 2kb User : r_ansal

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Source code to calculate the CRC of an incoming sequence of X bits.
Date : 2025-11-21 Size : 221kb User : jesortsan
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