VHDL-FPGA-Verilog List Page 2665

VHDL-FPGA-Verilog list

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design_dds_based_on_verilog Downloaded：0: The DDS-based design of verilog hdl
Date : 2025-11-22 Size : 388kb User : yangyang
COlD_FFT Downloaded：0: The VHDL implementation of 8-point FFT in VHDL. Radix 2 Decimation in Frequency It is very good
Date : 2025-11-22 Size : 63kb User : 小鸟动人
fft_design_in_VHDL Downloaded：0: Useful goods for FFT design I colected. Maybe useful for you. best wishes
Date : 2025-11-22 Size : 1.36mb User : 小鸟动人
VC Downloaded：0: Use the Verilog language to implement the FFT operation of 16 points. Use the Verilog language to implement the FFT operation of 16 points. Implement the FFT operation of 16 points in Verilog language. The Verilog langua
Date : 2025-11-22 Size : 5kb User : 懂郑华
DE2_Web_Server Downloaded：0: This file is Announces altera DE2 development board based on the-web routine, to achieve DE2 development board and the transfer of information between computers, using vhdL language.
Date : 2025-11-22 Size : 2.62mb User : 郝蕾
cunchuqi Downloaded：0: Using MAX+ PLUS for memory design
Date : 2025-11-22 Size : 37kb User : 白云
EDA Downloaded：0: Program counter, eda programming used, vhdl programming
Date : 2025-11-22 Size : 365kb User : 肄园
miaobiao Downloaded：0: 1. Design digital display of a stopwatch. 2. Can be accurately timed and displayed. 3. Power Show 00.00.00. 4. Users can always clear, pause, time. 5. 59.59.99 minutes maximum record time, the minimum accurate to 0.01 se
Date : 2025-11-22 Size : 1kb User : pp
multi-function_waveform_generator Downloaded：0: 4 sine wave to achieve common, triangle, sawtooth, square wave (A, B) the frequency and amplitude controlled output (square wave- A duty cycle is controllable), arbitrary waveform feature data can be stored and can re- i
Date : 2025-11-22 Size : 11kb User : 卫亮
Rake_Receiver Downloaded：1: Verilog HDL language with a Rake receiver maximum ratio combining criteria, of which 3 related to the parallel input data is output
Date : 2025-11-22 Size : 1kb User : 张茂磊
SOCKET Downloaded：0: De2-based development board and transfer between pc machine experiments, a detailed and comprehensive information on experimental procedures, socket program
Date : 2025-11-22 Size : 1.73mb User : 郝蕾
lcd Downloaded：0: SPARTAN 3E development board driver for digital circuit design, Verilog source code is a good reference
Date : 2025-11-22 Size : 2kb User : wang

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