VHDL-FPGA-Verilog List Page 2642

VHDL-FPGA-Verilog list

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UART Downloaded：0: uart interface written using Verilog, applicable to all FPGA
Date : 2025-11-22 Size : 3kb User : 潘映波
VGA Downloaded：0: VGA color bar generator, written using the Verilog
Date : 2025-11-22 Size : 315kb User : 潘映波
DDS Downloaded：0: Digital frequency meter DDS, prepared using the Verilog
Date : 2025-11-22 Size : 3kb User : 潘映波
ASKencoderanddecoder Downloaded：0: ASK encoder and decoder, the use of writing Verilog
Date : 2025-11-22 Size : 246kb User : 潘映波
ALU Downloaded：0: This experiment is based on arithmetic logical unit menu, to manually change the control signal combinations to achieve different arithmetic and logic functions, and the results that come out with the flag.
Date : 2025-11-22 Size : 51kb User : uu
DUI0455D_ambapv_dg Downloaded：0: AMBA-PV defines an extension, class amba_pv_extension, to the OSCI TLM 2.0 GP, class tlm_generic_payload.
Date : 2025-11-22 Size : 408kb User : hugo
uvm Downloaded：0: the Universal Verification Methodology (UVM) for creating SystemVerilog testbenches.
Date : 2025-11-22 Size : 6.78mb User : hugo
BIST Downloaded：0: A simple BIST in VHDL. It contains a LFSR with an SISR.
Date : 2025-11-22 Size : 396kb User : bommeren
pingpang Downloaded：0: Table tennis simulation game, enter a key debounce module, using two seven-segment digital tube to simulate the Table Tennis section 9 of the mobile line, cater to the middle of the digital net.
Date : 2025-11-22 Size : 293kb User : 李凡
FPGA_FIR Downloaded：0: FPGA-based FIR filter' s source code, the test is normal.
Date : 2025-11-22 Size : 149kb User : Nothing
traffic Downloaded：0: traffic light
Date : 2025-11-22 Size : 1.78mb User : 易阳威
fpgaex5 Downloaded：0: react time
Date : 2025-11-22 Size : 3.03mb User : 易阳威

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