VHDL-FPGA-Verilog List Page 2625

VHDL-FPGA-Verilog list

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PS2UART_verilog Downloaded：0: Based on Verilog, PS/2 keyboard interface, the receiving PS/2 keyboard data and convert it into ASCII code sent to the PC through the RS232 display.
Date : 2025-11-22 Size : 326kb User : liuxingxing
Altera-USB-Blaster-sch Downloaded：0: Production Altera USB-Blaster Schematic
Date : 2025-11-22 Size : 94kb User : liuxingxing
uart_regs Downloaded：0: an example for verilog
Date : 2025-11-22 Size : 920kb User : chenxiao
adc_master_0730 Downloaded：0: The driver circuit on the ADS7864 verilog code design, support Avalon bus
Date : 2025-11-22 Size : 2kb User : jacky
lcd_master_0607 Downloaded：0: LCD driver circuit on the THS12864 verilog code design, support Avalon bus
Date : 2025-11-22 Size : 1kb User : jacky
spi_master_0716 Downloaded：0: About four-wire SPI circuit verilog code design, support Avalon bus
Date : 2025-11-22 Size : 2kb User : jacky
key_master_0621 Downloaded：0: On the 4* 4 matrix keyboard scanning circuit verilog code design, support Avalon bus
Date : 2025-11-22 Size : 2kb User : jacky
wavelet Downloaded：1: Verilog DB8 Wavelet Transform Based on code design, support Avalon bus
Date : 2025-11-22 Size : 7kb User : jacky
FPGAtraining Downloaded：0: Yuan established FPGA technology training documentation
Date : 2025-11-22 Size : 1.46mb User : benben
sequential Downloaded：0: the simple verilog example, it is easy to starter to learn verilog
Date : 2025-11-22 Size : 8kb User : Roger
FPGAexampledesign Downloaded：0: Participated in the design competition with the FPGA when the routine, there should be a great reference! ! !
Date : 2025-11-22 Size : 12.04mb User : benben
ViterbiFPGA Downloaded：0: Discussion 了 CDMA digital mobile communication error control problems, research with the constraint degree K = 9 convolutional coding and maximum likelihood V iterbi error control coding scheme. In V iterbi decoding algo
Date : 2025-11-22 Size : 358kb User : tsincons

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