VHDL-FPGA-Verilog List Page 2618

VHDL-FPGA-Verilog list

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qdr2_sram Downloaded：0: qdr2 sram platform in the actual use of altera
Date : 2025-11-22 Size : 7.39mb User : dido wang
DDRSDRAMconclude Downloaded：0: DDR SDRAM DDR SDRAM Technical Summary describes some of the concepts and difficult to explain the mainstream DDRII technology focused on the final hardware design combined with some reference
Date : 2025-11-22 Size : 2.16mb User : 董萌
Miniproject_DSF_BATCH-30 Downloaded：0: source code for Sine wave generator using FPGA VHDL
Date : 2025-11-22 Size : 815kb User : SKA
lcd1602_drive Downloaded：0: About quartus.exe development program is implemented lcd1602 verilog source driver
Date : 2025-11-22 Size : 2kb User :
uart_rx Downloaded：0: quartus.exe edited and policy environment after the experiment as the FPGA device to receive data-driven serial port.
Date : 2025-11-22 Size : 1kb User :
eeprom_wr Downloaded：0: This program is quartus.exe edited and simulation environment after the eeprom in the protocol driver i2C
Date : 2025-11-22 Size : 3kb User :
Xming Downloaded：0: Xming X Server to configure and use, have been tested! Easy to use
Date : 2025-11-22 Size : 132kb User : wangnan
chuzuche Downloaded：0: The production of the final program FPGA taxi, automatic pricing feature.
Date : 2025-11-22 Size : 1.81mb User : 许凡
Piano Downloaded：0: Simple Piano generator - different frequencyis
Date : 2025-11-22 Size : 3kb User : yo Man
projektimikroprocesori Downloaded：0: microprocessor in VHDL
Date : 2025-11-22 Size : 141kb User : ina
CONTROL_DAC Downloaded：0: Seno Generator, for Altera DE2-70 This is a generator of seno signal and the output will be displayed in the VGA DAC of the board
Date : 2025-11-22 Size : 3kb User : Felix
Promediador Downloaded：0: This is a Promediator for the Altera DE2-2 it use a looktable for obtein the data and then promediates the current sample with 3 past samples.
Date : 2025-11-22 Size : 8kb User : Felix

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