VHDL-FPGA-Verilog List Page 2573

VHDL-FPGA-Verilog list

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decoder3_8 Downloaded：0: Vhdl language to achieve through a simple 3- 8 decoder making
Date : 2025-11-22 Size : 99kb User : 张哈
jiaotongdeng Downloaded：0: Achieved by using vhdl language design and manufacture of traffic lights
Date : 2025-11-22 Size : 38kb User : 张哈
serial_check Downloaded：0: In this study, need to implement a sequence detector, to detect whether the input serial bit stream and procedures consistent set of bit strings, if the same occurs in the verification of the waveform to represent a high
Date : 2025-11-22 Size : 49kb User : 张洁
four-bit-mul Downloaded：0: Achieved with the four adder tree multiplier multiplication
Date : 2025-11-22 Size : 126kb User : 张洁
coded-lock Downloaded：0: Design is a digital safe lock control circuit. First, the main problem is security, that is unlocking the password is likely to crack as small as possible followed by ease of operation, unlocking procedure but in the com
Date : 2025-11-22 Size : 119kb User : 张洁
max7000vgasync Downloaded：0: VHDL animation with simple codes
Date : 2025-11-22 Size : 1kb User : Azery
zlesson2BrA Downloaded：0: english for grammer fluency
Date : 2025-11-22 Size : 3.06mb User : siva ganesh malla
61EDA_D506 Downloaded：0: dwt of vhdl code
Date : 2025-11-22 Size : 1.41mb User : yangtianqi
SystemVerilog Downloaded：0: about systemverilog
Date : 2025-11-22 Size : 24kb User : liumeng
61EDA_C2442 Downloaded：0: ddr sdram
Date : 2025-11-22 Size : 15kb User : liumeng
61EDA_C2173 Downloaded：0: VHDL and cpu
Date : 2025-11-22 Size : 2kb User : liumeng
61EDA_C1910 Downloaded：0: ARM9 CORE achieve simple structure, can be integrated, with implementation steps and instructions, Verilog coding
Date : 2025-11-22 Size : 926kb User : liumeng

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