VHDL-FPGA-Verilog List Page 2523

VHDL-FPGA-Verilog list

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FPGAxiaoshufenpin Downloaded：0: ren yi xiao shu fen pin
Date : 2025-11-22 Size : 257kb User : jin
FP6182 Downloaded：0: PF6182 is a good DC-DC synchronous buck IC. Adjustable output voltage and current up to 2A. Very easy to use
Date : 2025-11-22 Size : 583kb User : longshiji
vhdl-digital-clock Downloaded：0: VHDL to implement digital electronic clock hours (24 hex), minutes and seconds (60 decimal) of the counting function with reset function expansion: a reset, the whole point timekeeping prompt, regular alarm clock functio
Date : 2025-11-22 Size : 76kb User : 陈添
VHDL-based-design-of-SPI Downloaded：0: VHDL-based SPI serial synchronous communication design as the design is the use of Quartus development environment to DE2 board as the hardware platform of the SPI synchronous serial communication. Facilitate the design
Date : 2025-11-22 Size : 50kb User : 陈添
zidongshouhuo Downloaded：0: Design a simple vending machine, the amount of money that it can complete the treatment, give change, display, coin and other functions. (1) with three keys that three kinds of money, and then 3 keys that 3 items. (2) di
Date : 2025-11-22 Size : 10kb User : chenbei
FACEDECTION Downloaded：0: Real times face detection
Date : 2025-11-22 Size : 3kb User : Nam
adder Downloaded：0: adder 32 is very easy to use adder 32 is make up by 4 adder 4 and i have nothing to say already~!
Date : 2025-11-22 Size : 774kb User : sofat
serial_adder Downloaded：0: This is a simple Serial Adder for Quartus II. The source code is in verilog HDL
Date : 2025-11-22 Size : 383kb User : Junkie
vga_focus_code Downloaded：0: PAL prepared using VHDL VGA format is converted to the source code, including the automatic zoom camera control source
Date : 2025-11-22 Size : 136kb User :
lattice_fpga Downloaded：0: good data for studying the lattice s fpga
Date : 2025-11-22 Size : 179kb User : 邱石
Desktop.tar Downloaded：0: I ve implemented what oi believe to be a very usefull and easy way to understand the FIFO queue using a DPRAM
Date : 2025-11-22 Size : 2kb User : andj
3-3-median-filter Downloaded：0: verilog fpga prepared for the 3x3 median filter template
Date : 2025-11-22 Size : 50kb User :

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