VHDL-FPGA-Verilog List Page 2513

VHDL-FPGA-Verilog list

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3344 Downloaded：0: BulkIn is the FPGA to send data to the CY7C68013 CY7C68013 BulkOut is receiving data from the FPGA
Date : 2025-11-22 Size : 289kb User : yangyang
5566 Downloaded：0: Alter official FFT program (written using Verilog)
Date : 2025-11-22 Size : 973kb User : yangyang
xuanze4x1 Downloaded：0: Based on VHDL, 4 to 1 MUX clock 48Mhz features 4 inputs can be only one output
Date : 2025-11-22 Size : 141kb User : 张帝
7788 Downloaded：0: Written in 1024 by verilog point fast Fourier transform fft
Date : 2025-11-22 Size : 12kb User : yangyang
99000 Downloaded：0: VerilogHDL Courseware good information can refer to
Date : 2025-11-22 Size : 1.27mb User : yangyang
dds2_ok Downloaded：0: HDL design using LPM_ROM and a DDS signal generator, the resolution is better than 1HZ, ROM table length 8 bits, 8-bit frequency control word.
Date : 2025-11-22 Size : 522kb User : 罗永
program Downloaded：0: 1/100s timer FPGA, the design of the timer to achieve the longest time show time of 1 minutes, 59.99 seconds, and the precision is greater than 1/100s, 1/100s timer can display the time.
Date : 2025-11-22 Size : 534kb User : sword
read-RAM Downloaded：0: Read and write RAM, is useful, I wrote it myself.
Date : 2025-11-22 Size : 598kb User : tanli
ajay-(1) Downloaded：0: fft fast fourier transform
Date : 2025-11-22 Size : 1kb User : Sridhar S
Timer Downloaded：0: This is a standed timer for an SOC design.It can realize multible function need to design an micro process circut
Date : 2025-11-22 Size : 5kb User : dreamhunter
lcd12864_test Downloaded：0: 12864 programs display with FPGA
Date : 2025-11-22 Size : 186kb User : yangshiqin
jiaotongdeng Downloaded：0: Simple traffic source code, vhdl programming. Straightforward. Reference for beginners.
Date : 2025-11-22 Size : 1kb User : 成杰

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