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VHDL-FPGA-Verilog list
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Lock can be password and the password comparison, the wrong password three times the lock and alarm
Date : 2025-11-23 Size : 732kb User : 李幸元

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Mux is designed by verilog use ISE of xilinx.have 4 input
Date : 2025-11-23 Size : 643kb User : Tầ n Long

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Using VHDL language, change traffic lights to achieve a crossroads, and has an emergency
Date : 2025-11-23 Size : 396kb User : duanhanshuo

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cache verilog for ARM
Date : 2025-11-23 Size : 3kb User : salvary

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VHDL cpu MUTIPYL ADD SUB JMP SHIFTL
Date : 2025-11-23 Size : 1.24mb User : 范志明

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VHDL cpu MUTIPYL ADD SUB JMP SHIFTL
Date : 2025-11-23 Size : 1.7mb User : 范志明

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Based on FPGA and DAC digital program-controlled amplifier and filter
Date : 2025-11-23 Size : 613kb User : lu

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Verilog language description of the VGA display experiment, the main purpose is to display 256 colors on the screen, useful for beginners
Date : 2025-11-23 Size : 502kb User : 老虎

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Verilog language description of the VGA display experiment, the main purpose is to display different characters on the screen, Quartus 10 in the compile.
Date : 2025-11-23 Size : 429kb User : 老虎

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Verilog language description, based on the design of the UART FIFO
Date : 2025-11-23 Size : 498kb User : 老虎

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Verilog language description, SRAM experimental operation, Quartus compiled by
Date : 2025-11-23 Size : 301kb User : 老虎

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VerilogHDL language code using the state machine, the proposed section is divided into three always
Date : 2025-11-23 Size : 602kb User : 老虎
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