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VHDL-FPGA-Verilog list
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NIOS-based HD system design, the article' s name is based on the NIOS high-resolution image acquisition system
Date : 2025-11-23 Size : 174kb User : liang ming

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A very practical, short AMI encoder, the output high for the sign bit, 1 for negative, 0 for positive
Date : 2025-11-23 Size : 4kb User : quanxuan

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booth multiplier test code booth testbench
Date : 2025-11-23 Size : 17kb User : jinglinde

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Taxi meter based on VHDL, VHDL language programming through the billing system of the four functional blocks: frequency module, control module, measuring module and decoding the display module, and finally use the MAX+ P
Date : 2025-11-23 Size : 1kb User : 张鹏飞

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PSPICE model of analog multiplier can be used Multisim simulation, etc.
Date : 2025-11-23 Size : 1kb User : Albert

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Car taillight controller, written by VHDL. Including simulation. Is a complete project
Date : 2025-11-23 Size : 101kb User :

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Written by VHDL sequence detector is a complete project.
Date : 2025-11-23 Size : 89kb User :

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UART module using Verilog
Date : 2025-11-23 Size : 1kb User : xhly

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code for ALU in singlecyclecpu
Date : 2025-11-23 Size : 208kb User : pardis88

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vhdl languages ​ debounce circuit for key debounce.
Date : 2025-11-23 Size : 1kb User :

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a iir filter model file
Date : 2025-11-23 Size : 9kb User : leo

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pll debug code,for quartus fpga,vhdl code for straxtix.
Date : 2025-11-23 Size : 3kb User : liuman
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