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VHDL-FPGA-Verilog list
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VHDL source frequency meter, frequency meter classic design, range 8.
Date : 2025-11-23 Size : 249kb User : 下世

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VHDL source code of traffic lights, respectively, with the main lane and the second lane, a choice of 4 kinds of state
Date : 2025-11-23 Size : 242kb User : 下世

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Digital clock in the VHDL source code, which the VHDL source code with a digital clock and schematic of the digital clock circuit digital clock with en, clk, clr and other interfaces.
Date : 2025-11-23 Size : 589kb User : 下世

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16* 16 dot matrix character scrolling display VHDL source. Chinese characters add their own words as needed.
Date : 2025-11-23 Size : 309kb User : 下世

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Spartan 3E development board Ethernet communications
Date : 2025-11-23 Size : 1.29mb User : 柳园

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Good examples on the ChipScope Pro Tutorial
Date : 2025-11-23 Size : 5.59mb User : 柳园

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12864 instructions specify how to display images in the corresponding complete display
Date : 2025-11-23 Size : 2kb User : 王瑞

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An ALU project in VHDL work perfectly
Date : 2025-11-23 Size : 172kb User : ezfn

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CycloneIIIFPGA detailed circuit boards
Date : 2025-11-23 Size : 258kb User : 姚龙海

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CPU configuration with Altera Corporation FPGA1
Date : 2025-11-23 Size : 13kb User : 姚龙海

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SP_RAM_16x8_TB_solution SRam 16x8 test bench solution. useful for verification.
Date : 2025-11-23 Size : 1kb User : gopi

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CPU configuration with Altera Corporation FPGA2
Date : 2025-11-23 Size : 342kb User : 姚龙海
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