VHDL-FPGA-Verilog List Page 218

VHDL-FPGA-Verilog list

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DE2_Default Downloaded：0: DE2 on-board testing code
Date : 2025-05-23 Size : 12kb User : tongjie
新建文件夹 Downloaded：0: Verilog yu yan bian xie de ying jian ding shi qi, qin ce gong neng ke yong
Date : 2025-05-23 Size : 3kb User : jiade
ckey_led7s Downloaded：1: Use buttons to control the display of digital tubes
Date : 2025-05-23 Size : 2.88mb User : 窈窕哥
ddr3_rw_ctrl Downloaded：1: it is based on DDR3 IP core of xilinx
Date : 2025-05-23 Size : 1kb User : superali
E_2011 Downloaded：0: A M sequence is generated that applies to the F question of the 2011 National Electronic Design Competition
Date : 2025-05-23 Size : 689kb User : 安珍妮
27_adda_test Downloaded：0: The ADDA module code applies to the black gold FPGA development board, the 35M sampling rate
Date : 2025-05-23 Size : 5.7mb User : 安珍妮
12864 Downloaded：0: The lcd12864 static display, cannot display the data in real time.
Date : 2025-05-23 Size : 2.32mb User : qwer_sun
cameralinkin_2_axis Downloaded：0: cameralink to axi_stream
Date : 2025-05-23 Size : 1kb User : 哈哈圈
flash_test Downloaded：0: FPGA read and write flash
Date : 2025-05-23 Size : 1kb User : xyheng
KEYPD Downloaded：0: Keypad sample. Vhdl language
Date : 2025-05-23 Size : 1kb User : Wens
JBD Downloaded：0: The basic D flip flops enable basic retention functions. Input to output remain unchanged.
Date : 2025-05-23 Size : 3kb User : 紫芩
T_0D Downloaded：0: D trigger module with synchronous clear 0 and synchronous setting 1. I hope I can help you.
Date : 2025-05-23 Size : 2.8mb User : 紫芩

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