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VHDL-FPGA-Verilog list
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main
Downloaded:0
HDMI1 sub-2 program-chip solution: IC EP9132 IC 74HC4052D debugging
Date
: 2025-11-24
Size
: 4kb
User
:
钱斌
uart-driver
Downloaded:0
STC12LE5A32S2 single-chip serial transceivers drive functions, including the serial read and write operations.
Date
: 2025-11-24
Size
: 1kb
User
:
张杰
uartrxto
Downloaded:0
STC12LE5A32S2 microcontroller serial port driver functions, the driver can send and receive function string function, with his assistant to send a string over the serial port, and then sent back to receive the string.
Date
: 2025-11-24
Size
: 67kb
User
:
张杰
rom_decoder_ram
Downloaded:0
Thirty-eight decoder
Date
: 2025-11-24
Size
: 340kb
User
:
王泽宇
singt
Downloaded:0
Based on fpga sinusoidal signal generator, VHDL language
Date
: 2025-11-24
Size
: 1kb
User
:
白羽
serial
Downloaded:0
Program realization fpga with the PC communications, verilog language
Date
: 2025-11-24
Size
: 3kb
User
:
白羽
verilog
Downloaded:0
verilog example of application is very wide, which contains almost all of the application examples, you learn a very good source of FPGA
Date
: 2025-11-24
Size
: 95kb
User
:
yu
SDRAM
Downloaded:0
timing of the SDRAM read and write verilog language description, a state machine structure to achieve read and write capabilities
Date
: 2025-11-24
Size
: 3kb
User
:
FIFO
Downloaded:0
This program is verilog language, functions as a FIFO function, consists of three parts, respectively, to achieve different functions.
Date
: 2025-11-24
Size
: 3kb
User
:
mcrmc
Downloaded:0
Wind power generation in the CPLD control panel reactive power compensation procedures for the preparation, mainly with the DSP and ARM timing control, and PWM wave generation.
Date
: 2025-11-24
Size
: 3kb
User
:
4fenpin
Downloaded:0
Achieve pulse source A, B phase is divided by 4 and 4 to achieve counting.
Date
: 2025-11-24
Size
: 672kb
User
:
尹秀清
FT245
Downloaded:0
The FPGA to implement a communication with the external USB FIFO FIFO control nuclear
Date
: 2025-11-24
Size
: 1kb
User
:
欧阳飞
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