VHDL-FPGA-Verilog List Page 211

VHDL-FPGA-Verilog list

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ac_acquire Downloaded：1: Ads127l01 series mode, in series with two chips, at this time the maximum sampling rate can not be used. The value of OSR is 01, 10, 11.
Date : 2025-05-22 Size : 1kb User : 纷飞血
LCD12864程序模块 Downloaded：0: Singlechip input to the above procedures, to achieve the driving function of LCD
Date : 2025-05-22 Size : 5kb User : 白马啸西风
fft fpga Downloaded：0: please copy this file very very good source code!!!!
Date : 2025-05-22 Size : 59kb User : jmc1988625
ex_DDS Downloaded：0: Verilog language based on DDS (digital frequency synthesizer) design, there is a complete engineering design code and simulation scripts
Date : 2025-05-22 Size : 7.16mb User : WaaDee
编译xilinx 库步骤 Downloaded：0: Compile the steps for the Xilinx Library
Date : 2025-05-22 Size : 602kb User : WaaDee
verilog_IEEE官方标准手册-2005_IEEE_P1364 Downloaded：0: Verilog_IEEE official standard manual, the internal details.
Date : 2025-05-22 Size : 2.04mb User : WaaDee
32位CPU IVERILOG源码 Downloaded：0: Describes how to implement 32 bit CPU in FPGA, involving the amount of IVERILOG source code
Date : 2025-05-22 Size : 75kb User : WaaDee
A4_Clock_Top Downloaded：0: 24 hours digital clock, can adjust time, can pause.
Date : 2025-05-22 Size : 3.62mb User : Hardware-engineer
A4_Uart_Top Downloaded：0: Provides the Uart communication protocol for the general FPGA development board
Date : 2025-05-22 Size : 6.3mb User : Hardware-engineer
蓝牙程序 Downloaded：0: ascacaavavavaDADASDAFAVAVVA
Date : 2025-05-22 Size : 1.84mb User : hahachi
四通道DDS信号发生器 Downloaded：0: Four-channel DDS signal generator
Date : 2025-05-22 Size : 6.48mb User : sauno
UART_FPGA Downloaded：0: Using VHDL to write the UART transceiver module
Date : 2025-05-22 Size : 144kb User : BY冬子

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