VHDL-FPGA-Verilog List Page 2081

VHDL-FPGA-Verilog list

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DES_VHDL Downloaded：0: DES VHDL FPGA CODING
Date : 2025-11-23 Size : 10.79mb User : 张彬
ZLG_CF Downloaded：0: CF CARD DRIVER FOR ZHOULIGONG NIOS
Date : 2025-11-23 Size : 205kb User : 张彬
VHDLdesignexamples Downloaded：0: Half-integer divider, music generator, signal generator, multi-function digital watch, traffic control lights, digital frequency meter design examples and exercises
Date : 2025-11-23 Size : 446kb User : 张怀卿
decimator Downloaded：0: Digital filter in delta-sigma ADC. But only work for RTL code now. Still have bugs in gate-level simulation.
Date : 2025-11-23 Size : 1kb User : DrCheese
led Downloaded：0: 51 single-chip digital control of the operation, the microcontroller Xinshoubikan learning materials.
Date : 2025-11-23 Size : 11kb User : 王晴
uart_rx Downloaded：0: From a computer to receive digital, in the middle bit of each received signal sample, and can determine the noise at the beginning. Download is over, the normal function
Date : 2025-11-23 Size : 106kb User : cherry
uart_tx Downloaded：0: Use the reset button on the FPGA input signal to output to the computer. Programming passed
Date : 2025-11-23 Size : 99kb User : cherry
VHDL Downloaded：0: Hardware description language (hardware description language, HDL) is the electronic system hardware behavior description, schema, data flow description language. Currently, the use of hardware description languages R
Date : 2025-11-23 Size : 59kb User : 司马大方
EET3350Lec14_shiftRegs Downloaded：0: EET 3350 Digital Systems Design.A register is a digital circuit with two basic functions: Data Storage and Data Movement A shift register provides the data movement function A shift register " shifts" its output
Date : 2025-11-23 Size : 2.01mb User : 司马大方
UART_Quartus_verilog Downloaded：0: Written in Verilog asynchronous serial communication program development environment for the Quartus II, with some reference value.
Date : 2025-11-23 Size : 2.72mb User : 杰
ad Downloaded：0: STC12C5A60S2 the AD converter, and into the LCD display
Date : 2025-11-23 Size : 1kb User : 张立
jing-dain--FPGA-cheng-xu Downloaded：0: Classical algorithm on the FPGA, including digital programming and display, using Verilog HDL language to write programs, the development board has been tested successfully!
Date : 2025-11-23 Size : 502kb User : chenfeihu

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