VHDL-FPGA-Verilog List Page 2060

VHDL-FPGA-Verilog list

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Coder Downloaded：0: 2-way video data plus 4-way serial data encoding and decoding, the system clock 30M
Date : 2025-11-23 Size : 405kb User : 张卫平
DDRPSDRAM-of-FPGA Downloaded：0: The VHDL source code contains detailed code can be modified directly used in your design,
Date : 2025-11-23 Size : 168kb User : ttfeng
CAN_jiedian Downloaded：0: CAN bus data are introduced, and with great enthusiasm got, very good, we can share with
Date : 2025-11-23 Size : 249kb User : peter
verilog Downloaded：0: CAN bus data are introduced, and with great enthusiasm got, very good, we can share with
Date : 2025-11-23 Size : 3kb User : peter
nnARM01_11_1_3 Downloaded：0: Contains detailed source code can be modified can be used in your design
Date : 2025-11-23 Size : 334kb User : ttfeng
1773bus Downloaded：0: Talking about some of the space application and development of the bus, the bus to do research on people who have some help
Date : 2025-11-23 Size : 154kb User : peter
NXPCAN Downloaded：0: CAN bus data are introduced, and with great enthusiasm got, very good, we can share with
Date : 2025-11-23 Size : 144kb User : peter
FIFO_buffer Downloaded：0: CAN bus data are introduced, and with great enthusiasm got, very good, we can share with
Date : 2025-11-23 Size : 1kb User : peter
fog_acc Downloaded：0: CAN bus data are introduced, and with great enthusiasm got, very good, we can share with
Date : 2025-11-23 Size : 1kb User : peter
usb2.0_funct_ip Downloaded：0: A USB2.0 IP core (for details verilog source code and documentation), it is a good reference design
Date : 2025-11-23 Size : 193kb User : 苏贺鹏
CPLD_RP Downloaded：0: Based on CPLD, counting function, optical encoder can be counted optical signal sent to the parallel port
Date : 2025-11-23 Size : 229kb User : shazhigang
LM2622 Downloaded：0: datasheet for dc-dc controller LM26
Date : 2025-11-23 Size : 281kb User : yuri

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