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VHDL-FPGA-Verilog list
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addr4
Downloaded:0
Can achieve four full adder, full adder using four series were not as fast carry bit of the way
Date
: 2025-09-19
Size
: 3kb
User
:
刘芳
Electronic-clock
Downloaded:0
VHDL language with a 24-band electronic clock, which set up some key changes in values, etc.
Date
: 2025-09-19
Size
: 2kb
User
:
苏鸿
02_fenpinqi
Downloaded:0
Simple wording divider module, for beginners to learn the FPGA
Date
: 2025-09-19
Size
: 303kb
User
:
丁剑
mult
Downloaded:0
Verilog HDL language with 16-bit multiplier, and tesrbench (test file).
Date
: 2025-09-19
Size
: 1kb
User
:
jiyun
elevmain
Downloaded:0
Signal Vs Variable difference code in VHDL
Date
: 2025-09-19
Size
: 29kb
User
:
neeraj
FEC-in-DTV
Downloaded:0
FEC solution in digital TV application
Date
: 2025-09-19
Size
: 656kb
User
:
YangYG
verilog_-key_board-scan
Downloaded:0
Can be 4 × 4 keypad numbers 0_9 display to LED, press the 4 × 4 on the keyboard when a key figure 0_9, LED digital tube can be displayed on the corresponding number key
Date
: 2025-09-19
Size
: 5kb
User
:
guoying
ep1c6_29_dds
Downloaded:0
Digital adjustment of the frequency, the structure is simple, feasible, and high accuracy.
Date
: 2025-09-19
Size
: 562kb
User
:
陈冠霖
ep1c6_38_fft_test
Downloaded:0
Digital adjustment of the frequency, the structure is simple, feasible, and high accuracy.
Date
: 2025-09-19
Size
: 504kb
User
:
陈冠霖
ep1c6_37_fir_test
Downloaded:0
Digital adjustment of the frequency, the structure is simple, feasible, and high accuracy.
Date
: 2025-09-19
Size
: 215kb
User
:
陈冠霖
ep1c6_34_ps2_mouse_test
Downloaded:0
Digital adjustment of the frequency, the structure is simple, feasible, and high accuracy.
Date
: 2025-09-19
Size
: 154kb
User
:
陈冠霖
ep1c6_35_ps2_keyboard_test
Downloaded:0
Digital adjustment of the frequency, the structure is simple, feasible, and high accuracy.
Date
: 2025-09-19
Size
: 175kb
User
:
陈冠霖
«
1
2
...
.78
.79
.80
.81
.82
1983
.84
.85
.86
.87
.88
...
4310
»
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