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VHDL-FPGA-Verilog list
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seqdet
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Sequence detector design
Date : 2025-11-23 Size : 25kb User : zhangxina
ambe_rf
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Wrote AMBE100 controller using verilog code style is very good, simple and powerful, test code is also to facilitate the exchange
Date : 2025-11-23 Size : 18kb User : 林文兴
Verilog
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Based on various examples written in verilog HDL. . Recording the counter, full adder, and so the code.
Date : 2025-11-23 Size : 242kb User : 黄灿灿
Traffic-Light-Controller
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Verilog language realization the design of the traffic lights
Date : 2025-11-23 Size : 19kb User : zhangxina
Gerhard-Fettweis-at-BWRC-2009-09-18
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Signal processing and its implementation for LTE-Advanced
Date : 2025-11-23 Size : 7.92mb User : saravanan
hahatu
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The FPGA to the VGA output of the correct timing, in modified and embedded into your project which you can view the VGA timing.
Date : 2025-11-23 Size : 1.19mb User : DMANO
MyDDR
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Analysis of how to control the FPGA DDR, this method is its frequency multiplier rather than the process inside the handle into the IPCORE
Date : 2025-11-23 Size : 8.99mb User : DMANO
sram1
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This the simplest control SRAM FPGA one of the methods can be nested directly to your code, look at the timing analysis proposed
Date : 2025-11-23 Size : 147kb User : DMANO
dead
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PWM waveform inversion, and the dead zone settings. Verification process is correct.
Date : 2025-11-23 Size : 3kb User : 孔令军
CRC-8
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VHDL code for CRC-8 computing using 32 bit input (parallel)
Date : 2025-11-23 Size : 1kb User : stefanovic
fifo
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cy7c68013 fifo code can be realized in the configuration
Date : 2025-11-23 Size : 3kb User : dingxing
cy7c68013fpga_code
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cy7c68013 the fpga configuration code, verilog syntax
Date : 2025-11-23 Size : 369kb User : dingxing
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