VHDL-FPGA-Verilog List Page 1886

VHDL-FPGA-Verilog list

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Touch-Screen_code Downloaded：0: Touch-screen code, you can download to try to see wheter it fit your application
Date : 2025-09-18 Size : 2kb User : yeqy
example-of-verilog-design Downloaded：0: verilog a large number of examples, including some commonly used digital circuit design, very practical
Date : 2025-09-18 Size : 111kb User : yeqy
Matlab-Verilog-Linking Downloaded：0: Matlab Verilog Linking super full of teaching, you can try
Date : 2025-09-18 Size : 2.26mb User : yeqy
texisystem Downloaded：0: Single-chip microcomputer as the central controller, the design of a taxi meter system. System in the DC source is vehicle power supply, power supply voltage of+9 V ~+24 V. No mileage sensor design, assuming it has a car
Date : 2025-09-18 Size : 53kb User : yangzhen
DE2_SD_Card_Audio Downloaded：0: Read SD Card based on the DE2 board,the environment is nios ii IDE
Date : 2025-09-18 Size : 24.8mb User : Wu Hao
texi Downloaded：0: Single-chip microcomputer as the central controller, the design of a taxi meter system. System in the DC source is vehicle power supply, power supply voltage of+9 V ~+24 V. No mileage sensor design, assuming it has a car
Date : 2025-09-18 Size : 73kb User : yangzhen
texismoke Downloaded：0: Single-chip microcomputer as the central controller, the design of a taxi meter system. System in the DC source is vehicle power supply, power supply voltage of+9 V ~+24 V. No mileage sensor design, assuming it has a car
Date : 2025-09-18 Size : 51kb User : yangzhen
ppt4aix4sopc Downloaded：0: powerpoint for aix4 sopc development
Date : 2025-09-18 Size : 1.2mb User : sunking
est_rm Downloaded：0: Latest xilinx edk 13.2 software development Resources for microblaze system development
Date : 2025-09-18 Size : 1.55mb User : sunking
VHDL_piano Downloaded：0: The entire code using VHDL language, simulation with experimental box, very practical, can be used directly
Date : 2025-09-18 Size : 6kb User : 薛鹏展
sdram_vhdl Downloaded：0: DDR (double rate) SDRAM controller reference design Verilog code, can be directly used, very good.
Date : 2025-09-18 Size : 871kb User : 薛鹏展
AT24C04VHDL Downloaded：0: With the Verilog HDL language of the AT24C04 procedures and use digital tube display, has been tested, very good to use.
Date : 2025-09-18 Size : 12kb User : 薛鹏展

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