VHDL-FPGA-Verilog List Page 1702

VHDL-FPGA-Verilog list

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VerilogHDLshuzizhong Downloaded：0: The design of the digital clock, required to display format for hours-minutes-seconds, respectively in eight seven LED digital tube for dynamic points the way to scan showed that additional features: when the tastemaker
Date : 2025-09-15 Size : 106kb User : 张伟
myprogram Downloaded：0: File packages that contain and FPGA and serial interface communication related procedures and tutorial to the study of FPGA to have the help very much.
Date : 2025-09-15 Size : 56.77mb User : jamysun
addN Downloaded：0: A simple ADDN module
Date : 2025-09-15 Size : 1kb User : ntsoa
FREQ Downloaded：0: The program use verilog programming language, realized the frequency meter
Date : 2025-09-15 Size : 22.34mb User : 杨慧
Embedded_System_Lab Downloaded：0: Tutorial on Embedded Systems with NIOS II, SOPCBuilder and Quartus II.
Date : 2025-09-15 Size : 1.34mb User : rponguil
DCT8_final Downloaded：0: 2D-dctThe FPGA realizing algorithm
Date : 2025-09-15 Size : 7kb User : 鸿哲
DCT Downloaded：0: 2D-dctThe FPGA realizing algorithm
Date : 2025-09-15 Size : 7kb User : 鸿哲
Development-QuanGongLve1 Downloaded：0: FPGA development QuanGongLve ， the good learning FPGA information
Date : 2025-09-15 Size : 6.35mb User : 李帅
2dDCT Downloaded：0: 2D-dct The FPGA realizing algorithm
Date : 2025-09-15 Size : 7kb User : 鸿哲
Development-QuanGongLve2 Downloaded：0: FPGA development QuanGongLve， the good learning FPGA information
Date : 2025-09-15 Size : 4.22mb User : 李帅
SOPC Downloaded：0: SOPC Development quick how-to tutorials Chinese version
Date : 2025-09-15 Size : 1.94mb User : 李帅
encoder_Z64_all_rate Downloaded：0: Wimax based LDPC encoder, modelsim simulation passed, also passed on altera FPGA board, code rate 5/6, also support 2/3,3/4, throughout 700m
Date : 2025-09-15 Size : 220kb User : 姜勇吉

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