VHDL-FPGA-Verilog List Page 1646

VHDL-FPGA-Verilog list

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GSM Downloaded：0: PROGRAM TO TAKE DATA FROM ADC AND TRANSMIT USING GSM.
Date : 2025-09-14 Size : 42kb User : VIJAY
SPEED_CONTROL_OF_BLDC_MOTOR_PWM Downloaded：0: brush less dc motor control
Date : 2025-09-14 Size : 14kb User : VIJAY
FPGA-traffic-light Downloaded：0: design of traffic light based on FPGA,use the veriog HDL language.
Date : 2025-09-14 Size : 1kb User : 夏勇
verilog-tutorial Downloaded：0: Huawei verilog tutorial for beginners
Date : 2025-09-14 Size : 260kb User : snowman
VHDL--TESTBENCH Downloaded：0: The use of VHDL to write TESTBENCH files.useful for new people
Date : 2025-09-14 Size : 9.16mb User : 姜珊
RS232 Downloaded：0: This code has been verified in the experimental panel, 9600 baud, clock 50MHz.
Date : 2025-09-14 Size : 4.75mb User : lida
spilicheng Downloaded：0: spi interface wishbone bus, to achieve the basic functions of the spi controller to book routine
Date : 2025-09-14 Size : 2.15mb User : 在
FPGA-TOP-TOWN Downloaded：0: FPGA/EPLD ( Top-Down ) top-down design method
Date : 2025-09-14 Size : 49kb User : 文杰
FLASH_16PWM Downloaded：0: The C8051F340 developed PWM program, we hope to help.
Date : 2025-09-14 Size : 44kb User : 李百良
UART0 Downloaded：0: The C8051F340 developed UART program, we hope to help.
Date : 2025-09-14 Size : 20kb User : 李百良
UART0_ADC Downloaded：0: The C8051F340 developed UART&ADC program, we hope to help.
Date : 2025-09-14 Size : 33kb User : 李百良
sy5 Downloaded：0: LIBRARY IEEE USE IEEE.STD_LOGIC_1164.ALL ENTITY ADCINT IS PORT(D : IN STD_LOGIC_VECTOR(7 DOWNTO 0) --来自0809转换好的8位数据 CLK : IN STD_LOGIC --状态机工作时钟 EOC : IN STD_LOGIC --转换状态指示，低电平表示正在转换 ALE : OUT STD_LOGIC --8个模拟信号通道地址锁存信号
Date : 2025-09-14 Size : 2kb User : 镜辰

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