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VHDL-FPGA-Verilog list
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Downloaded:0
8-3 multiplexer fpga realize, digital tube display the currently selected data Numbers
Date
: 2025-09-13
Size
: 9kb
User
:
cc
add
Downloaded:0
Four parallel QuanJia device fpga realizing by 4 a QuanJia emulators, and a leading sensor into binary, can carry up
Date
: 2025-09-13
Size
: 25kb
User
:
cc
add_4
Downloaded:0
Four series of fpga realizing the QuanJia by 4 a QuanJia emulators
Date
: 2025-09-13
Size
: 12kb
User
:
cc
autoseller
Downloaded:0
AUTOSELLER
Date
: 2025-09-13
Size
: 520kb
User
:
david
based-on-Xilinx-PCIe-Core-DMA
Downloaded:1
1, 支持由板卡发起的DMA操作,既可以将板卡内的数据快速传输到PC,也可以将PC的数据读取到板卡内。DMA的可以通过PCIe的BAR0空间控制。 2, 利用Xilinx LogiCORE Endpoint Block Plus硬核,兼容Virtex 5、Virtex 6、Spartan 6系列。无缝支持PCIe x8、x4、x1速率 。 3, 在板卡的终端是标准的FIFO接口,可以接入各种形式的数据,例如AD采样数据,光纤数据,DA数
Date
: 2025-09-13
Size
: 2.22mb
User
:
rosen
15-piano
Downloaded:0
This is a successful organ VHDL source code, in the DH-33001 development board debugging.
Date
: 2025-09-13
Size
: 76kb
User
:
hjs
01-halfadd
Downloaded:0
This a successful half-adder VHDL source code, in the DH-33001 development board debugging.
Date
: 2025-09-13
Size
: 33kb
User
:
hjs
04-led
Downloaded:0
This is a successful control LED display of VHDL and Verilog source code, in the DH-33 001 development board debugging.
Date
: 2025-09-13
Size
: 33kb
User
:
hjs
13-traffic
Downloaded:0
This a successful traffic lights VHDL and Verilog source code, in the DH-33 001 development board debugging.
Date
: 2025-09-13
Size
: 804kb
User
:
hjs
17-Clock
Downloaded:0
This is a successful electronic clock VHDL and Verilog source code, in the DH-33 001 development board debugging.
Date
: 2025-09-13
Size
: 80kb
User
:
hjs
Sequential-detection
Downloaded:0
Sequential detection
Date
: 2025-09-13
Size
: 1kb
User
:
lmy
qiangdaqi
Downloaded:0
Described is a 8 bit responder, believe to be helpful for beginners
Date
: 2025-09-13
Size
: 3kb
User
:
«
1
2
...
.71
.72
.73
.74
.75
1576
.77
.78
.79
.80
.81
...
4310
»
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