VHDL-FPGA-Verilog List Page 1476

VHDL-FPGA-Verilog list

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urunn_length_s Downloaded：0: With verilog development for image compression using run length encoding (run lengthencoding, RLE) coding to encode the exchange coefficient (Aa).

Date : 2025-09-11 Size : 9kb User : 举例
51 Downloaded：0: 51 MCU clock program (call display routines to improve the LED display flicker)
Date : 2025-09-11 Size : 8kb User : penghuifu
cnt24 Downloaded：0: 24 hex counter
Date : 2025-09-11 Size : 3kb User : Tom
25c Downloaded：0: Based on the xilinx spartan 3e development boards of ATMEL 25c Department of class EEPROM interface program. The EEPROM values can be read out and displayed on the LCD. Read frequency is controlled by the D
Date : 2025-09-11 Size : 1.57mb User : 李华
93c Downloaded：0: Xilinx spartan 3e development boards of ATMEL 93c Department of class (46 56 66) EEPROM interface program. The EEPROM values can be read out and displayed on the LCD. Read frequency is controlled by the DCM
Date : 2025-09-11 Size : 583kb User : 李华
TS_i2c Downloaded：0: Based on the xilinx spartan 3e development boards CAT34TS02 AT30TSE002B TS part of the test program with a temperature sensor EEPROM. Write data through the serial port and address. Keys control the internal register val
Date : 2025-09-11 Size : 1.04mb User : 李华
lab3NHHT Downloaded：0: Lab Project On MISP single cycle implementation
Date : 2025-09-11 Size : 331kb User : Anh Tuan
FileRecv Downloaded：0: Convolutional code introduced the paper, as well as the Matlab code
Date : 2025-09-11 Size : 1.27mb User : 钟鑫
shizhong Downloaded：0: FPGA Design- Best Practices
Date : 2025-09-11 Size : 485kb User : 李宁
VGA Downloaded：0: FPGA Design- Best Practices
Date : 2025-09-11 Size : 427kb User : 李宁
IIC Downloaded：0: FPGA Design- Best Practices
Date : 2025-09-11 Size : 612kb User : 李宁
Verilg-135samples Downloaded：0: FPGA Design- Best Practices
Date : 2025-09-11 Size : 112kb User : 李宁

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