VHDL-FPGA-Verilog List Page 1422

VHDL-FPGA-Verilog list

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8b10b_encdec_latest.tar Downloaded：0: This file 8b10b encoding test program can be directly simulated. Including encoding, decoding the complete code.
Date : 2025-09-10 Size : 132kb User : 党领茹
tcpudp Downloaded：0: Niosii environment, through the establishment of the SPI core to drive the Ethernet controller enc28j60 embedded tcp/ip protocol to the network port communications.
Date : 2025-09-10 Size : 33kb User : 胡思兵
7_ren_biao_jue_qi Downloaded：0: VHDL design of a seven-vote in favor of the number of greater than or equal to four o' clock, the vote at the same time, respectively, displayed the number of people vote in favor of and against the number of digital
Date : 2025-09-10 Size : 441kb User : sam
NIOS_II Downloaded：0: NIOS II development of the frequently asked questions, common errors and solutions
Date : 2025-09-10 Size : 14kb User : sam
ping_pong_game Downloaded：0: with the Using of DaltaSigma DAC principle, the output to the oscilloscope XY channel to display the bright spot mapping table tennis game.
Date : 2025-09-10 Size : 11.19mb User :
scope_VGA Downloaded：0: IIC interface 4-way ADC max1037, collecting ideas signal the FPGA internal build DeltaSigma DAC soft-core VGA LCD display waveforms.
Date : 2025-09-10 Size : 3.76mb User :
dlx_verilog Downloaded：0: The use the verilog voice development of the dlx Reduced Instruction Set, simple functions, suitable for beginners to learn.
Date : 2025-09-10 Size : 10kb User : kean
sdram_control Downloaded：0: sdram control.write and read
Date : 2025-09-10 Size : 8.99mb User : 刘向阳
ss Downloaded：0: verilog language design M-sequence-based codec
Date : 2025-09-10 Size : 17kb User : 宋锴
systolic--matrix-inversion Downloaded：0: Architecture and design of DSP algorithms, based on systolic upper triangular matrix inverse circuit to achieve detailed MATLAB/SIMULINK model and the HDL code in modelsim simulation program, which is very good.
Date : 2025-09-10 Size : 1.32mb User :
signal_generator Downloaded：0: The signal generator can generate through the program corresponding to the waveform using the Verilog language
Date : 2025-09-10 Size : 419kb User : 于梦磊
FPGA Downloaded：0: FPGA manual, including the 430, ds001 the function module is introduced, and so on.
Date : 2025-09-10 Size : 1.48mb User : 谢文华

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