VHDL-FPGA-Verilog List Page 127

VHDL-FPGA-Verilog list

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Xilinx的增量编译技术 Downloaded：0: Incremental compilation technology, the basic principle is based on the results of the previous compilation, only re-editing part of the modified design, the other part is based on the results of the previous compilation
Date : 2025-05-18 Size : 67kb User : 小旦
elevator Downloaded：0: Control system of elevator operation
Date : 2025-05-18 Size : 1kb User : proud
ADC_Data_Recv_Module Downloaded：0: The receiver tests the input signal, Generation of positive cosine wave, sampling rate, frequency, amplitude, phase can be adjusted And output the generated data The compressed package includes the Verilog code, the test
Date : 2025-05-18 Size : 500kb User : nokkk
Clock_Synchronization_Module Downloaded：0: Design of medium frequency digital clock in digital receiver Including Matlab simulation Verilog, testbench code, and design documents
Date : 2025-05-18 Size : 240kb User : nokkk
FFT_Module Downloaded：1: The code of the digital part FFT module of the receiver Including Verilog, matlab simulation, testbench Implementation of FFT
Date : 2025-05-18 Size : 5.72mb User : nokkk
Orthogonization_Module Downloaded：1: Receiver digital part orthogonal frequency mixing module ' Including Verilog code Matlab simulation Testbench code
Date : 2025-05-18 Size : 1.71mb User : nokkk
CIC_Filter_Module Downloaded：1: CIC decimation module of digital receiver Extraction multiple can be selected Including Verilog code Word document Matlab simulation Testbench code
Date : 2025-05-18 Size : 2.87mb User : nokkk
FRJ_HN1702_Assignment3_ThangNN6 Downloaded：0: Horizontal size of Unix machines. The latest name of the AS400 is the IBM Iseries (I = Integrated), which is integrated because it is sold with all the pre-installed programs. The AS400 is aimed at mid-market companies,
Date : 2025-05-18 Size : 1.11mb User : haifdfdf
6_key_test Downloaded：0: The keys on the keyboard, Quartus keyboard scanning based on Verilog implementation
Date : 2025-05-18 Size : 3.01mb User : 木头心儿
8_uart_test Downloaded：0: Serial communication and serial communication with Verilog based on Quartus
Date : 2025-05-18 Size : 10.76mb User : 木头心儿
VerilogHDL硬件描述语言 Downloaded：0: Verilog language introductory course, detailing the Verilog syntax and Application
Date : 2025-05-18 Size : 2.95mb User : Arwen_yuan
22_xiaodou Downloaded：0: Key elimination jitter based on FPGA function implementation
Date : 2025-05-18 Size : 3mb User : ZXC1211267519

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