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VHDL-FPGA-Verilog list
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LC2K
Downloaded:0
It is a design of CPU of "little computer" in VHDL.
Date
: 2025-08-26
Size
: 6kb
User
:
张治国
DDS_AD9854_For_FPGA
Downloaded:0
DDS_AD9854_for FPGA, verilog source code, signal generator.
Date
: 2025-08-26
Size
: 196kb
User
:
胡彤
dab1814114c3
Downloaded:0
File/Directory Description ============================================================================= \doc DDR SDRAM reference design documentation \model Contains the verilog SDRAM model \route Contains the Quartus
Date
: 2025-08-26
Size
: 860kb
User
:
李志偉
BAO_TP2
Downloaded:0
VHDL code for a simple CPU model-based, contains ten originals. River Comprehensive simulation has been
Date
: 2025-08-26
Size
: 7kb
User
:
包包
7053590045826
Downloaded:0
De2 development board lcm screen as part of the verification code to share with you
Date
: 2025-08-26
Size
: 1.27mb
User
:
付神九
1226133460_ddvip_5499
Downloaded:0
DE2 development board information useful for students to be able to open the inside on the development board is quite thin
Date
: 2025-08-26
Size
: 1.66mb
User
:
付神九
8.22-出租车计价器VHDL程序与仿真
Downloaded:0
Taximeter procedures and VHDL simulation, the file is a word file inside the source code, program description, and the simulation results in Fig.
Date
: 2025-08-26
Size
: 84kb
User
:
张林
Flying-Adder
Downloaded:0
VHDL Code and Some Images for Flying-Adder Frequency Synthesizer. It s a All-digital Novel Structure.
Date
: 2025-08-26
Size
: 80kb
User
:
张震
Digital-Photo-Frame
Downloaded:0
EP1C3T144 and sdram-based digital photo frame
Date
: 2025-08-26
Size
: 15kb
User
:
梁愈高
jiaotongdeng
Downloaded:0
Traffic lights (non-mainstream the simple wording Edition): design an intersection traffic light control circuit, the alternating A the driveway and B lane two cross road vehicles running each passing time set to 25 seco
Date
: 2025-08-26
Size
: 409kb
User
:
张小栗
led_liushuideng
Downloaded:0
Midway variable speed and flowers rich LED light water can continue to add in the source statement flowers richer
Date
: 2025-08-26
Size
: 367kb
User
:
张小栗
filter
Downloaded:0
FIR digital filter design based on VHDL, can modify the parameters to set the filter order
Date
: 2025-08-26
Size
: 1.77mb
User
:
123
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.36
.37
.38
.39
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1241
.42
.43
.44
.45
.46
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4310
»
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