VHDL-FPGA-Verilog List Page 1218

VHDL-FPGA-Verilog list

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Tate_Bilinear_Pairing_latest.tar Downloaded：0: The Tate Bilinear Pairing core is for calculating Tate bilinear pairing especially on super-singular elliptic curve in affine coordinates defined over a Galois field , whose irreducible polynomial is . (For improving sec
Date : 2025-08-25 Size : 482kb User : ke
tiny_tate_bilinear_pairing_latest.tar Downloaded：0: Tiny Tate Bilinear Pairing core is for calculating a special type of Tate bilinear pairing called reduced pairing.
Date : 2025-08-25 Size : 1.07mb User : ke
openmsp430_latest.tar Downloaded：0: The openMSP430 is a 16-bit microcontroller core compatible with TI s MSP430 family (note that the extended version of the architecture, the MSP430X, isn t supported by this IP). It is based on a Von Neumann architecture,
Date : 2025-08-25 Size : 36.25mb User : ke
Amber_ARM-compatible_core_latest.tar Downloaded：0: The Amber processor core is an ARM-compatible 32-bit RISC processor. The Amber core is fully compatible with the ARM ® v2a instruction set architecture (ISA) and is therefore supported by the GNU toolset. This older
Date : 2025-08-25 Size : 3.44mb User : ke
t400u_latest.tar Downloaded：0: The T400u controller is an implementation of National s 4-bit COP400 microcontroller family architecture. It is intended to be used as a replacement for the original chip in SOCs recreating legacy systems. Its final targ
Date : 2025-08-25 Size : 502kb User : ke
t48u_latest.tar Downloaded：0: The T48 μController core is an implementation of the MCS-48 microcontroller family ar-chitecture. While being a controller core for SoC, it also aims for code-compatability and cycle-accuracy so that it can be used as a
Date : 2025-08-25 Size : 4.01mb User : ke
jiance1 Downloaded：0: The XOR output cycle pseudo-random number generator
Date : 2025-08-25 Size : 1kb User : 陈治斌
数码管 Verilog Downloaded：0: verilog 设计电路将计算结果显示在数码管上
Date : 2013-03-02 Size : 1.12kb User : yanpengzhan
final_PLL_130T_240Mhz Downloaded：0: Verilog debugging the LMX2541, on board test normal! Single-frequency output SPI control.
Date : 2025-08-25 Size : 2.14mb User : lianggui
sobel2 Downloaded：0: The sobel operator new FPGA implementation. Verilog language, and debugging through to
Date : 2025-08-25 Size : 348kb User : abrams
median_filter Downloaded：0: Median filter verilog achieve complete engineering, debugging through
Date : 2025-08-25 Size : 2.75mb User : abrams
uart Downloaded：0: UART serial port transceiver procedures VHDL
Date : 2025-08-25 Size : 2kb User : 蒋坤

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