VHDL-FPGA-Verilog List Page 1211

VHDL-FPGA-Verilog list

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multiplier-experiment Downloaded：0: The ZLG Fusion StartKit, fpga development board test routines, the constant coefficient multiplier experiment
Date : 2025-08-22 Size : 1mb User : xyz
Verilog-basic-program Downloaded：0: study nios
Date : 2025-08-22 Size : 1.3mb User : 好好
verilog_17_usb_device Downloaded：0: verilog study
Date : 2025-08-22 Size : 4kb User : 好好
1.Area-Efficient-Carry-Select-Adder Downloaded：0: Area efficient carry save adder
Date : 2025-08-22 Size : 197kb User : arev
ade Downloaded：0: Verilog code for modified serial multiplier
Date : 2025-08-22 Size : 1kb User : arev
Adder Downloaded：0: 8bit low power pipelined adder
Date : 2025-08-22 Size : 1kb User : arev
SDRAM_Source Downloaded：0: DE2 Board SDRAM Controller
Date : 2025-08-22 Size : 12kb User : choi
SDRAM Downloaded：0: DE2 SDRAM Controller Pin Configuration Set
Date : 2025-08-22 Size : 1.17mb User : choi
RS232 Downloaded：0: DE2 Board RS232(UART CHIP Level)
Date : 2025-08-22 Size : 513kb User : choi
FLASH Downloaded：0: DE2 Board FLASH Memory Controller
Date : 2025-08-22 Size : 915kb User : choi
viterbi-deoder Downloaded：0: viterbi decoder with constraint length 7,4
Date : 2025-08-22 Size : 1kb User : arev
booth.vhd Downloaded：0: this the source code for booth s multiplier. used to low power dsp architecture.
Date : 2025-08-22 Size : 1kb User : nathan

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