[Other] 0-10Sud

Description: 0-10 sound files, application programmers calculator voice use, or when the number of voice reported.
Platform: | Size: 39438 | Author: 普乐 | Hits:

[JSP/Java] javawork

Description: This code is a simple stock analysis system, divided into server and client at both ends, customers can see from the client end of the current stock price information, and systematic editors from the server-side only to
Platform: | Size: 11126 | Author: 林金漢 | Hits:

[FlashMX] flash

Description: Self-developed simple FLASH animation, music and through a simple screen can be seen that the art of life, and easy to modify
Platform: | Size: 8573962 | Author: 林金漢 | Hits:

[Other resource] dt-VHDL

Description: Function of elevator controller This elevator controller is divided into main controller and sub-controller. The main controller is the controller inside the elevator, and each floor has a sub-controller. Functions of ma
Platform: | Size: 164122 | Author: que | Hits:

[Other resource] 10gamesofj2meformobiephone

Description: Mobile game 10 classic mobile game source code complete source code, can run and can be realized
Platform: | Size: 3970038 | Author: 王宗祥 | Hits:

[Other resource] Proteus.Professional.7.1.SP2

Description: Proteus.Professional.7.1.SP2. Introduce new features in detail. Pdf
Platform: | Size: 161148 | Author: huang | Hits:

[Other resource] MSP430

Description: MSP430 series single chip is c language source code, introduce 430 commonly used c program
Platform: | Size: 373862 | Author: 李世民 | Hits:

[Other resource] uart

Description: M_UART introduce a Universal Asynchronous Receiver Transmitter (UART) Principle and FPGA programmable logic device as the core control unit, based on the ultra-high-speed hardware description language VHDL in Xilinx
Platform: | Size: 18918 | Author: lc | Hits:

[Other] fsm

Description: FSM state machine, this document provides a relatively simple state machine by the FSM as a programming example
Platform: | Size: 2294 | Author: 陈轩辕 | Hits:

[Other resource] Lab1_FPGA

Description: lab1- FPGA decency in this document on how to how to use the verilog Hdl and how to make it realize in FPGA development board
Platform: | Size: 146766 | Author: 陈轩辕 | Hits:

[Windows Develop] aes

Description: DES algorithm aes is an important development, we can see his zoyong
Platform: | Size: 4378 | Author: 萧芬 | Hits:

[Other resource] Ultraedit_verilog

Description: This document provides a verilog hdl in ultra edit32 programming required in grammar
Platform: | Size: 31182 | Author: 陈轩辕 | Hits: