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PT100 measurement circuit and measurement method for high-precision design and development
Date : 2008-10-13 Size : 7.33kb User : 王涛

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The use of chain store realize one of the following polynomial operation: (1), the basic requirements: the realization of polynomial addition, subtraction, derivation. (2), the realization of polynomial multiplication
Date : 2008-10-13 Size : 16.46kb User : 姜华

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MSP430
Date : 2008-10-13 Size : 21.49kb User : 王涛

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Data interleaver verilog HDL source file
Date : 2008-10-13 Size : 98.25kb User : 长空

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Create a sequence table: the output sequence table: the order of the output of various elements insertion sequence table: Insert in the designated location element delete the order form: delete the specified location in
Date : 2008-10-13 Size : 28.97kb User : 姜华

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Frame Synchronization Verilog HDL source code to achieve synchronization receiver
Date : 2008-10-13 Size : 75.44kb User : 长空

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To look at a few simple wrl model, you need Come under
Date : 2008-10-13 Size : 2.46mb User : lvkun

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Many things in this program can be configured in the data section Configurable square size, color, interface location, use of keys, each square model shape You can configure the shape of each square model to change, and
Date : 2008-10-13 Size : 4.55kb User : 张磊

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Cyclic Redundancy Check realize Verilog source code
Date : 2008-10-13 Size : 359.06kb User : 长空

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Used realize adder VerilogHDL Le Hua domain adder
Date : 2008-10-13 Size : 189.53kb User : 长空

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This is an article on BP neural network and genetic algorithm combination of papers, and they hope to be helpful to everyone!
Date : 2008-10-13 Size : 3.18mb User : hou gui yun

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Users in the application memory allocation must take into account the memory allocation and memory release
Date : 2008-10-13 Size : 145.23kb User : hsr
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