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spdgevd Downloaded：0: this code calculate how to trace image
Date : 2025-09-26 Size : 3kb User : HARKATI
someip_generator Downloaded：0: python code for someip analyser
Date : 2025-09-26 Size : 42kb User : huwenguo
pyECU Downloaded：0: python code for generator of the ECU Model in automobil
Date : 2025-09-26 Size : 111kb User : huwenguo
tsort Downloaded：0: this code calculate how to trace image
Date : 2025-09-26 Size : 2kb User : HARKATI
controller Downloaded：0: Simple Microprocessor Design (ESD Book Chapter 3) Copyright 2001 Weijun Zhang Controller (control logic plus state register) VHDL FSM modeling
Date : 2025-09-26 Size : 2kb User : mohamed
memory Downloaded：0: Simple Microprocessor Design memory 256*16 8 bit address 16 bit data memory.vhd
Date : 2025-09-26 Size : 1kb User : mohamed
DSP Downloaded：0: FIR Digital Filter Design (DSP example) tested by Weijun Zhang, 04/2001 VHDL Data-Flow modeling KEYWORD: generate, array, range, constant and subtype
Date : 2025-09-26 Size : 1kb User : mohamed
Controller(FSM) Downloaded：0: Simple Bridge (ESD book figure 2.14) by Weijun Zhang, 04/2001 RT level design using Controller(FSM) + DataPath
Date : 2025-09-26 Size : 2kb User : mohamed
GCD-CALCULATOR Downloaded：0: GCD CALCULATOR (ESD book figure 2.11) Weijun Zhang, 04/2001 we can put all the components in one document(gcd2.vhd) or put them in separate files this is the example of RT level modeling (FSM + DataPath) the code is syn
Date : 2025-09-26 Size : 2kb User : mohamed
seperate_kernel_standard Downloaded：0: it is to make a 3 dimentional function be expressed as three 1 dimntional funtions
Date : 2025-09-26 Size : 23kb User : lynn
yuhui Downloaded：1: CGH detour phase encoding is a very important way of coding, which involves a lot of knowledge of Fourier
Date : 2025-09-26 Size : 1kb User : 赵自新
BER_computation_in_AWGN Downloaded：0: Matlab/Octave script for simulating BER for BPSK modulation in AWGN chnanel.
Date : 2025-09-26 Size : 1kb User : 潜伏

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