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18_uart Downloaded：0: Realized through the establishment of the module s serial verilog on FPGA
Date : 2025-09-27 Size : 5.83mb User : gaoyong
qoufen Downloaded：0: Decoupling, restore the original signal, A relatively before correction and after correction PMUSIC, Undergraduate complete set requirements refer to the standard test models.
Date : 2025-09-27 Size : 5kb User : 杨占科
saifai Downloaded：0: Normalized data model, modal vibration, Using common plane wave expansion method, Comparison of soft threshold and hard threshold and today various threshold calculation method.
Date : 2025-09-27 Size : 6kb User : 王小
J2.S.P0021 Downloaded：0: puzzle game using java base one algorithms
Date : 2025-09-27 Size : 45kb User : tan
sanlan Downloaded：0: matlab development toolbox support vector machine, Correlation analysis process matlab method, Based on wavelet transform digital watermarking algorithm matlab code.
Date : 2025-09-27 Size : 8kb User : 李胜发
saohai_v68 Downloaded：0: It comprises aircraft flight attitude control, such as slip angle, tilt angle, roll angle, pitch angle, By matlab code, It contains positional PID algorithm, integral separate PID.
Date : 2025-09-27 Size : 4kb User : 李胜发
Form1 Downloaded：0: Basically realize the import of music files, click on the play, click on the play and click on the next song, click to stop playing music
Date : 2025-09-27 Size : 1kb User : 王苗姜
VGA_pic_200x200x3(ok) Downloaded：0: Altera series FPGA to achieve the VGA display 8 color images, debugging through, the development environment QuartusII, language verilog.
Date : 2025-09-27 Size : 6.56mb User : PrudentMe
seifen_v35 Downloaded：0: Can dynamically adjust the parameters of the operating environment, Including orbital maneuvering simulation, initial orbit calculation, Calculating a target and ocean echo power spectral density.
Date : 2025-09-27 Size : 8kb User : 毛百国
seiqou_v17 Downloaded：0: Based on the time delay estimation of power spectrum, Debugging can be used, PSS primary synchronization signal in the time domain simulation related.
Date : 2025-09-27 Size : 8kb User : 毛百国
VDL Downloaded：0: Static compiler tools, support for VDL static editing
Date : 2025-09-27 Size : 10.79mb User : 275012469
DDS(ok) Downloaded：0: Make ROM sine table and fill the ROM internal FPGA, by calling the internal data to achieve the sine wave output, development environment QuartusII, Language Verilog, debugging through, with Modelsim debugging results.
Date : 2025-09-27 Size : 9.68mb User : PrudentMe

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