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Binary-tree Downloaded：0: Create a binary tree, in order of first-order recursive post-order binary tree, find the number of leaves, tree height requirements, exchange of left and right subtrees.
Date : 2025-05-25 Size : 2kb User : zhoulu
select Downloaded：0: Functions to achieve the election of the roll call and determine who was selected
Date : 2025-05-25 Size : 13mb User : youkai
tank Downloaded：0: 90 sees, java version, to achieve a variety of tank operation
Date : 2025-05-25 Size : 5kb User : 宜阳
irda_rx Downloaded：0: Infrared transceiver receiver module, very very strong. Using Verilog design and simulation using Modelsim, function entirely correct.
Date : 2025-05-25 Size : 4.51mb User : iswl2009
SPP Downloaded：0: GPS S
Date : 2025-05-25 Size : 213kb User : tengliu
aeroFrame Downloaded：0: Achieved through a simple statement like win7' s aero effects, which also includes some other simple operation interface
Date : 2025-05-25 Size : 2kb User : 黄花菜
fft_32 Downloaded：0: FFT is complemented by Vhdl.
Date : 2025-05-25 Size : 4kb User : 郭晓阳
par_in_par_out Downloaded：0: Into the shift register and a two-way, very very strong. With Verilog for design and simulation using Modelsim successfully.
Date : 2025-05-25 Size : 1.21mb User : iswl2009
par_in_ser_out Downloaded：0: Into the string of registers, very strong. With Verilog for design and simulation using Modelsim successfully.
Date : 2025-05-25 Size : 1.39mb User : iswl2009
ser_in_per_out Downloaded：0: String into register, very strong. With Verilog for design and simulation using Modelsim successfully.
Date : 2025-05-25 Size : 1.64mb User : iswl2009
Freescale-Tsinghua-technical-report Downloaded：0: 第一界飞思卡尔冠军清华二队技术报告
Date : 2025-05-25 Size : 957kb User : 赵炜
ser_in_ser_out Downloaded：0: String into the string of bi-directional shift register, very very strong. With Verilog for design and simulation using Modelsim successfully.
Date : 2025-05-25 Size : 1.33mb User : iswl2009

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